xref: /rk3399_ARM-atf/plat/nvidia/tegra/common/tegra_sip_calls.c (revision e40e075f4ddf63aa84d2aaacb807ed40438f1d24)
1 /*
2  * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * Redistributions of source code must retain the above copyright notice, this
8  * list of conditions and the following disclaimer.
9  *
10  * Redistributions in binary form must reproduce the above copyright notice,
11  * this list of conditions and the following disclaimer in the documentation
12  * and/or other materials provided with the distribution.
13  *
14  * Neither the name of ARM nor the names of its contributors may be used
15  * to endorse or promote products derived from this software without specific
16  * prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28  * POSSIBILITY OF SUCH DAMAGE.
29  */
30 
31 #include <arch.h>
32 #include <arch_helpers.h>
33 #include <assert.h>
34 #include <bl_common.h>
35 #include <debug.h>
36 #include <errno.h>
37 #include <memctrl.h>
38 #include <runtime_svc.h>
39 #include <tegra_private.h>
40 
41 /*******************************************************************************
42  * Common Tegra SiP SMCs
43  ******************************************************************************/
44 #define TEGRA_SIP_NEW_VIDEOMEM_REGION		0x82000003
45 
46 /*******************************************************************************
47  * SoC specific SiP handler
48  ******************************************************************************/
49 #pragma weak plat_sip_handler
50 int plat_sip_handler(uint32_t smc_fid,
51 		     uint64_t x1,
52 		     uint64_t x2,
53 		     uint64_t x3,
54 		     uint64_t x4,
55 		     void *cookie,
56 		     void *handle,
57 		     uint64_t flags)
58 {
59 	return -ENOTSUP;
60 }
61 
62 /*******************************************************************************
63  * This function is responsible for handling all SiP calls from the NS world
64  ******************************************************************************/
65 uint64_t tegra_sip_handler(uint32_t smc_fid,
66 			   uint64_t x1,
67 			   uint64_t x2,
68 			   uint64_t x3,
69 			   uint64_t x4,
70 			   void *cookie,
71 			   void *handle,
72 			   uint64_t flags)
73 {
74 	uint32_t ns;
75 	int err;
76 
77 	/* Determine which security state this SMC originated from */
78 	ns = is_caller_non_secure(flags);
79 	if (!ns)
80 		SMC_RET1(handle, SMC_UNK);
81 
82 	/* Check if this is a SoC specific SiP */
83 	err = plat_sip_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
84 	if (err == 0)
85 		SMC_RET1(handle, err);
86 
87 	switch (smc_fid) {
88 
89 	case TEGRA_SIP_NEW_VIDEOMEM_REGION:
90 
91 		/* clean up the high bits */
92 		x1 = (uint32_t)x1;
93 		x2 = (uint32_t)x2;
94 
95 		/*
96 		 * Check if Video Memory overlaps TZDRAM (contains bl31/bl32)
97 		 * or falls outside of the valid DRAM range
98 		 */
99 		err = bl31_check_ns_address(x1, x2);
100 		if (err)
101 			SMC_RET1(handle, err);
102 
103 		/*
104 		 * Check if Video Memory is aligned to 1MB.
105 		 */
106 		if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) {
107 			ERROR("Unaligned Video Memory base address!\n");
108 			SMC_RET1(handle, -ENOTSUP);
109 		}
110 
111 		/* new video memory carveout settings */
112 		tegra_memctrl_videomem_setup(x1, x2);
113 
114 		SMC_RET1(handle, 0);
115 		break;
116 
117 	default:
118 		ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
119 		break;
120 	}
121 
122 	SMC_RET1(handle, SMC_UNK);
123 }
124 
125 /* Define a runtime service descriptor for fast SMC calls */
126 DECLARE_RT_SVC(
127 	tegra_sip_fast,
128 
129 	OEN_SIP_START,
130 	OEN_SIP_END,
131 	SMC_TYPE_FAST,
132 	NULL,
133 	tegra_sip_handler
134 );
135