1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <bl_common.h> 35 #include <debug.h> 36 #include <errno.h> 37 #include <memctrl.h> 38 #include <runtime_svc.h> 39 #include <tegra_private.h> 40 41 /******************************************************************************* 42 * Common Tegra SiP SMCs 43 ******************************************************************************/ 44 #define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003 45 #define TEGRA_SIP_FIQ_NS_ENTRYPOINT 0x82000005 46 #define TEGRA_SIP_FIQ_NS_GET_CONTEXT 0x82000006 47 48 /******************************************************************************* 49 * SoC specific SiP handler 50 ******************************************************************************/ 51 #pragma weak plat_sip_handler 52 int plat_sip_handler(uint32_t smc_fid, 53 uint64_t x1, 54 uint64_t x2, 55 uint64_t x3, 56 uint64_t x4, 57 void *cookie, 58 void *handle, 59 uint64_t flags) 60 { 61 return -ENOTSUP; 62 } 63 64 /******************************************************************************* 65 * This function is responsible for handling all SiP calls 66 ******************************************************************************/ 67 uint64_t tegra_sip_handler(uint32_t smc_fid, 68 uint64_t x1, 69 uint64_t x2, 70 uint64_t x3, 71 uint64_t x4, 72 void *cookie, 73 void *handle, 74 uint64_t flags) 75 { 76 int err; 77 78 /* Check if this is a SoC specific SiP */ 79 err = plat_sip_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); 80 if (err == 0) 81 SMC_RET1(handle, err); 82 83 switch (smc_fid) { 84 85 case TEGRA_SIP_NEW_VIDEOMEM_REGION: 86 87 /* clean up the high bits */ 88 x2 = (uint32_t)x2; 89 90 /* 91 * Check if Video Memory overlaps TZDRAM (contains bl31/bl32) 92 * or falls outside of the valid DRAM range 93 */ 94 err = bl31_check_ns_address(x1, x2); 95 if (err) 96 SMC_RET1(handle, err); 97 98 /* 99 * Check if Video Memory is aligned to 1MB. 100 */ 101 if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) { 102 ERROR("Unaligned Video Memory base address!\n"); 103 SMC_RET1(handle, -ENOTSUP); 104 } 105 106 /* new video memory carveout settings */ 107 tegra_memctrl_videomem_setup(x1, x2); 108 109 SMC_RET1(handle, 0); 110 break; 111 112 /* 113 * The NS world registers the address of its handler to be 114 * used for processing the FIQ. This is normally used by the 115 * NS FIQ debugger driver to detect system hangs by programming 116 * a watchdog timer to fire a FIQ interrupt. 117 */ 118 case TEGRA_SIP_FIQ_NS_ENTRYPOINT: 119 120 if (!x1) 121 SMC_RET1(handle, SMC_UNK); 122 123 /* 124 * TODO: Check if x1 contains a valid DRAM address 125 */ 126 127 /* store the NS world's entrypoint */ 128 tegra_fiq_set_ns_entrypoint(x1); 129 130 SMC_RET1(handle, 0); 131 break; 132 133 /* 134 * The NS world's FIQ handler issues this SMC to get the NS EL1/EL0 135 * CPU context when the FIQ interrupt was triggered. This allows the 136 * NS world to understand the CPU state when the watchdog interrupt 137 * triggered. 138 */ 139 case TEGRA_SIP_FIQ_NS_GET_CONTEXT: 140 141 /* retrieve context registers when FIQ triggered */ 142 tegra_fiq_get_intr_context(); 143 144 SMC_RET0(handle); 145 break; 146 147 default: 148 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 149 break; 150 } 151 152 SMC_RET1(handle, SMC_UNK); 153 } 154 155 /* Define a runtime service descriptor for fast SMC calls */ 156 DECLARE_RT_SVC( 157 tegra_sip_fast, 158 159 OEN_SIP_START, 160 OEN_SIP_END, 161 SMC_TYPE_FAST, 162 NULL, 163 tegra_sip_handler 164 ); 165