1*d288ab24SVarun Wadekar /* 2*d288ab24SVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3*d288ab24SVarun Wadekar * 4*d288ab24SVarun Wadekar * Redistribution and use in source and binary forms, with or without 5*d288ab24SVarun Wadekar * modification, are permitted provided that the following conditions are met: 6*d288ab24SVarun Wadekar * 7*d288ab24SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 8*d288ab24SVarun Wadekar * list of conditions and the following disclaimer. 9*d288ab24SVarun Wadekar * 10*d288ab24SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 11*d288ab24SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 12*d288ab24SVarun Wadekar * and/or other materials provided with the distribution. 13*d288ab24SVarun Wadekar * 14*d288ab24SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 15*d288ab24SVarun Wadekar * to endorse or promote products derived from this software without specific 16*d288ab24SVarun Wadekar * prior written permission. 17*d288ab24SVarun Wadekar * 18*d288ab24SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*d288ab24SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*d288ab24SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*d288ab24SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*d288ab24SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*d288ab24SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*d288ab24SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*d288ab24SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*d288ab24SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*d288ab24SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*d288ab24SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 29*d288ab24SVarun Wadekar */ 30*d288ab24SVarun Wadekar 31*d288ab24SVarun Wadekar #include <arch.h> 32*d288ab24SVarun Wadekar #include <arch_helpers.h> 33*d288ab24SVarun Wadekar #include <assert.h> 34*d288ab24SVarun Wadekar #include <bl_common.h> 35*d288ab24SVarun Wadekar #include <debug.h> 36*d288ab24SVarun Wadekar #include <errno.h> 37*d288ab24SVarun Wadekar #include <memctrl.h> 38*d288ab24SVarun Wadekar #include <runtime_svc.h> 39*d288ab24SVarun Wadekar #include <tegra_private.h> 40*d288ab24SVarun Wadekar 41*d288ab24SVarun Wadekar /******************************************************************************* 42*d288ab24SVarun Wadekar * Common Tegra SiP SMCs 43*d288ab24SVarun Wadekar ******************************************************************************/ 44*d288ab24SVarun Wadekar #define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003 45*d288ab24SVarun Wadekar 46*d288ab24SVarun Wadekar /******************************************************************************* 47*d288ab24SVarun Wadekar * SoC specific SiP handler 48*d288ab24SVarun Wadekar ******************************************************************************/ 49*d288ab24SVarun Wadekar #pragma weak plat_sip_handler 50*d288ab24SVarun Wadekar int plat_sip_handler(uint32_t smc_fid, 51*d288ab24SVarun Wadekar uint64_t x1, 52*d288ab24SVarun Wadekar uint64_t x2, 53*d288ab24SVarun Wadekar uint64_t x3, 54*d288ab24SVarun Wadekar uint64_t x4, 55*d288ab24SVarun Wadekar void *cookie, 56*d288ab24SVarun Wadekar void *handle, 57*d288ab24SVarun Wadekar uint64_t flags) 58*d288ab24SVarun Wadekar { 59*d288ab24SVarun Wadekar return -ENOTSUP; 60*d288ab24SVarun Wadekar } 61*d288ab24SVarun Wadekar 62*d288ab24SVarun Wadekar /******************************************************************************* 63*d288ab24SVarun Wadekar * This function is responsible for handling all SiP calls from the NS world 64*d288ab24SVarun Wadekar ******************************************************************************/ 65*d288ab24SVarun Wadekar uint64_t tegra_sip_handler(uint32_t smc_fid, 66*d288ab24SVarun Wadekar uint64_t x1, 67*d288ab24SVarun Wadekar uint64_t x2, 68*d288ab24SVarun Wadekar uint64_t x3, 69*d288ab24SVarun Wadekar uint64_t x4, 70*d288ab24SVarun Wadekar void *cookie, 71*d288ab24SVarun Wadekar void *handle, 72*d288ab24SVarun Wadekar uint64_t flags) 73*d288ab24SVarun Wadekar { 74*d288ab24SVarun Wadekar uint32_t ns; 75*d288ab24SVarun Wadekar int err; 76*d288ab24SVarun Wadekar 77*d288ab24SVarun Wadekar /* Determine which security state this SMC originated from */ 78*d288ab24SVarun Wadekar ns = is_caller_non_secure(flags); 79*d288ab24SVarun Wadekar if (!ns) 80*d288ab24SVarun Wadekar SMC_RET1(handle, SMC_UNK); 81*d288ab24SVarun Wadekar 82*d288ab24SVarun Wadekar /* Check if this is a SoC specific SiP */ 83*d288ab24SVarun Wadekar err = plat_sip_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); 84*d288ab24SVarun Wadekar if (err == 0) 85*d288ab24SVarun Wadekar SMC_RET1(handle, err); 86*d288ab24SVarun Wadekar 87*d288ab24SVarun Wadekar switch (smc_fid) { 88*d288ab24SVarun Wadekar 89*d288ab24SVarun Wadekar case TEGRA_SIP_NEW_VIDEOMEM_REGION: 90*d288ab24SVarun Wadekar 91*d288ab24SVarun Wadekar /* clean up the high bits */ 92*d288ab24SVarun Wadekar x1 = (uint32_t)x1; 93*d288ab24SVarun Wadekar x2 = (uint32_t)x2; 94*d288ab24SVarun Wadekar 95*d288ab24SVarun Wadekar /* 96*d288ab24SVarun Wadekar * Check if Video Memory overlaps TZDRAM (contains bl31/bl32) 97*d288ab24SVarun Wadekar * or falls outside of the valid DRAM range 98*d288ab24SVarun Wadekar */ 99*d288ab24SVarun Wadekar err = bl31_check_ns_address(x1, x2); 100*d288ab24SVarun Wadekar if (err) 101*d288ab24SVarun Wadekar SMC_RET1(handle, err); 102*d288ab24SVarun Wadekar 103*d288ab24SVarun Wadekar /* 104*d288ab24SVarun Wadekar * Check if Video Memory is aligned to 1MB. 105*d288ab24SVarun Wadekar */ 106*d288ab24SVarun Wadekar if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) { 107*d288ab24SVarun Wadekar ERROR("Unaligned Video Memory base address!\n"); 108*d288ab24SVarun Wadekar SMC_RET1(handle, -ENOTSUP); 109*d288ab24SVarun Wadekar } 110*d288ab24SVarun Wadekar 111*d288ab24SVarun Wadekar /* new video memory carveout settings */ 112*d288ab24SVarun Wadekar tegra_memctrl_videomem_setup(x1, x2); 113*d288ab24SVarun Wadekar 114*d288ab24SVarun Wadekar SMC_RET1(handle, 0); 115*d288ab24SVarun Wadekar break; 116*d288ab24SVarun Wadekar 117*d288ab24SVarun Wadekar default: 118*d288ab24SVarun Wadekar ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 119*d288ab24SVarun Wadekar break; 120*d288ab24SVarun Wadekar } 121*d288ab24SVarun Wadekar 122*d288ab24SVarun Wadekar SMC_RET1(handle, SMC_UNK); 123*d288ab24SVarun Wadekar } 124*d288ab24SVarun Wadekar 125*d288ab24SVarun Wadekar /* Define a runtime service descriptor for fast SMC calls */ 126*d288ab24SVarun Wadekar DECLARE_RT_SVC( 127*d288ab24SVarun Wadekar tegra_sip_fast, 128*d288ab24SVarun Wadekar 129*d288ab24SVarun Wadekar OEN_SIP_START, 130*d288ab24SVarun Wadekar OEN_SIP_END, 131*d288ab24SVarun Wadekar SMC_TYPE_FAST, 132*d288ab24SVarun Wadekar NULL, 133*d288ab24SVarun Wadekar tegra_sip_handler 134*d288ab24SVarun Wadekar ); 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