1d288ab24SVarun Wadekar /* 2*a9e0260cSVignesh Radhakrishnan * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3d288ab24SVarun Wadekar * 4d288ab24SVarun Wadekar * Redistribution and use in source and binary forms, with or without 5d288ab24SVarun Wadekar * modification, are permitted provided that the following conditions are met: 6d288ab24SVarun Wadekar * 7d288ab24SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 8d288ab24SVarun Wadekar * list of conditions and the following disclaimer. 9d288ab24SVarun Wadekar * 10d288ab24SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 11d288ab24SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 12d288ab24SVarun Wadekar * and/or other materials provided with the distribution. 13d288ab24SVarun Wadekar * 14d288ab24SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 15d288ab24SVarun Wadekar * to endorse or promote products derived from this software without specific 16d288ab24SVarun Wadekar * prior written permission. 17d288ab24SVarun Wadekar * 18d288ab24SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19d288ab24SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20d288ab24SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21d288ab24SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22d288ab24SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23d288ab24SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24d288ab24SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25d288ab24SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26d288ab24SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27d288ab24SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28d288ab24SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 29d288ab24SVarun Wadekar */ 30d288ab24SVarun Wadekar 31d288ab24SVarun Wadekar #include <arch.h> 32d288ab24SVarun Wadekar #include <arch_helpers.h> 33d288ab24SVarun Wadekar #include <assert.h> 34d288ab24SVarun Wadekar #include <bl_common.h> 35d288ab24SVarun Wadekar #include <debug.h> 36d288ab24SVarun Wadekar #include <errno.h> 37d288ab24SVarun Wadekar #include <memctrl.h> 38d288ab24SVarun Wadekar #include <runtime_svc.h> 39d288ab24SVarun Wadekar #include <tegra_private.h> 40*a9e0260cSVignesh Radhakrishnan #include <tegra_platform.h> 41d288ab24SVarun Wadekar 42d288ab24SVarun Wadekar /******************************************************************************* 43d288ab24SVarun Wadekar * Common Tegra SiP SMCs 44d288ab24SVarun Wadekar ******************************************************************************/ 45d288ab24SVarun Wadekar #define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003 4678e2bd10SVarun Wadekar #define TEGRA_SIP_FIQ_NS_ENTRYPOINT 0x82000005 4778e2bd10SVarun Wadekar #define TEGRA_SIP_FIQ_NS_GET_CONTEXT 0x82000006 48*a9e0260cSVignesh Radhakrishnan #define TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND 0xC2000007 49*a9e0260cSVignesh Radhakrishnan 50*a9e0260cSVignesh Radhakrishnan /******************************************************************************* 51*a9e0260cSVignesh Radhakrishnan * Fake system suspend mode control var 52*a9e0260cSVignesh Radhakrishnan ******************************************************************************/ 53*a9e0260cSVignesh Radhakrishnan extern uint8_t tegra_fake_system_suspend; 54*a9e0260cSVignesh Radhakrishnan 55d288ab24SVarun Wadekar 56d288ab24SVarun Wadekar /******************************************************************************* 57d288ab24SVarun Wadekar * SoC specific SiP handler 58d288ab24SVarun Wadekar ******************************************************************************/ 59d288ab24SVarun Wadekar #pragma weak plat_sip_handler 60d288ab24SVarun Wadekar int plat_sip_handler(uint32_t smc_fid, 61d288ab24SVarun Wadekar uint64_t x1, 62d288ab24SVarun Wadekar uint64_t x2, 63d288ab24SVarun Wadekar uint64_t x3, 64d288ab24SVarun Wadekar uint64_t x4, 65d288ab24SVarun Wadekar void *cookie, 66d288ab24SVarun Wadekar void *handle, 67d288ab24SVarun Wadekar uint64_t flags) 68d288ab24SVarun Wadekar { 69d288ab24SVarun Wadekar return -ENOTSUP; 70d288ab24SVarun Wadekar } 71d288ab24SVarun Wadekar 72d288ab24SVarun Wadekar /******************************************************************************* 732d05f810SWayne Lin * This function is responsible for handling all SiP calls 74d288ab24SVarun Wadekar ******************************************************************************/ 75d288ab24SVarun Wadekar uint64_t tegra_sip_handler(uint32_t smc_fid, 76d288ab24SVarun Wadekar uint64_t x1, 77d288ab24SVarun Wadekar uint64_t x2, 78d288ab24SVarun Wadekar uint64_t x3, 79d288ab24SVarun Wadekar uint64_t x4, 80d288ab24SVarun Wadekar void *cookie, 81d288ab24SVarun Wadekar void *handle, 82d288ab24SVarun Wadekar uint64_t flags) 83d288ab24SVarun Wadekar { 84d288ab24SVarun Wadekar int err; 85d288ab24SVarun Wadekar 86d288ab24SVarun Wadekar /* Check if this is a SoC specific SiP */ 87d288ab24SVarun Wadekar err = plat_sip_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); 88d288ab24SVarun Wadekar if (err == 0) 89d288ab24SVarun Wadekar SMC_RET1(handle, err); 90d288ab24SVarun Wadekar 91d288ab24SVarun Wadekar switch (smc_fid) { 92d288ab24SVarun Wadekar 93d288ab24SVarun Wadekar case TEGRA_SIP_NEW_VIDEOMEM_REGION: 94d288ab24SVarun Wadekar 95d288ab24SVarun Wadekar /* clean up the high bits */ 96d288ab24SVarun Wadekar x2 = (uint32_t)x2; 97d288ab24SVarun Wadekar 98d288ab24SVarun Wadekar /* 99d288ab24SVarun Wadekar * Check if Video Memory overlaps TZDRAM (contains bl31/bl32) 100d288ab24SVarun Wadekar * or falls outside of the valid DRAM range 101d288ab24SVarun Wadekar */ 102d288ab24SVarun Wadekar err = bl31_check_ns_address(x1, x2); 103d288ab24SVarun Wadekar if (err) 104d288ab24SVarun Wadekar SMC_RET1(handle, err); 105d288ab24SVarun Wadekar 106d288ab24SVarun Wadekar /* 107d288ab24SVarun Wadekar * Check if Video Memory is aligned to 1MB. 108d288ab24SVarun Wadekar */ 109d288ab24SVarun Wadekar if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) { 110d288ab24SVarun Wadekar ERROR("Unaligned Video Memory base address!\n"); 111d288ab24SVarun Wadekar SMC_RET1(handle, -ENOTSUP); 112d288ab24SVarun Wadekar } 113d288ab24SVarun Wadekar 114d288ab24SVarun Wadekar /* new video memory carveout settings */ 115d288ab24SVarun Wadekar tegra_memctrl_videomem_setup(x1, x2); 116d288ab24SVarun Wadekar 117d288ab24SVarun Wadekar SMC_RET1(handle, 0); 118d288ab24SVarun Wadekar break; 119d288ab24SVarun Wadekar 12078e2bd10SVarun Wadekar /* 12178e2bd10SVarun Wadekar * The NS world registers the address of its handler to be 12278e2bd10SVarun Wadekar * used for processing the FIQ. This is normally used by the 12378e2bd10SVarun Wadekar * NS FIQ debugger driver to detect system hangs by programming 12478e2bd10SVarun Wadekar * a watchdog timer to fire a FIQ interrupt. 12578e2bd10SVarun Wadekar */ 12678e2bd10SVarun Wadekar case TEGRA_SIP_FIQ_NS_ENTRYPOINT: 12778e2bd10SVarun Wadekar 12878e2bd10SVarun Wadekar if (!x1) 12978e2bd10SVarun Wadekar SMC_RET1(handle, SMC_UNK); 13078e2bd10SVarun Wadekar 13178e2bd10SVarun Wadekar /* 13278e2bd10SVarun Wadekar * TODO: Check if x1 contains a valid DRAM address 13378e2bd10SVarun Wadekar */ 13478e2bd10SVarun Wadekar 13578e2bd10SVarun Wadekar /* store the NS world's entrypoint */ 13678e2bd10SVarun Wadekar tegra_fiq_set_ns_entrypoint(x1); 13778e2bd10SVarun Wadekar 13878e2bd10SVarun Wadekar SMC_RET1(handle, 0); 13978e2bd10SVarun Wadekar break; 14078e2bd10SVarun Wadekar 14178e2bd10SVarun Wadekar /* 14278e2bd10SVarun Wadekar * The NS world's FIQ handler issues this SMC to get the NS EL1/EL0 14378e2bd10SVarun Wadekar * CPU context when the FIQ interrupt was triggered. This allows the 14478e2bd10SVarun Wadekar * NS world to understand the CPU state when the watchdog interrupt 14578e2bd10SVarun Wadekar * triggered. 14678e2bd10SVarun Wadekar */ 14778e2bd10SVarun Wadekar case TEGRA_SIP_FIQ_NS_GET_CONTEXT: 14878e2bd10SVarun Wadekar 14978e2bd10SVarun Wadekar /* retrieve context registers when FIQ triggered */ 15078e2bd10SVarun Wadekar tegra_fiq_get_intr_context(); 15178e2bd10SVarun Wadekar 15278e2bd10SVarun Wadekar SMC_RET0(handle); 15378e2bd10SVarun Wadekar break; 15478e2bd10SVarun Wadekar 155*a9e0260cSVignesh Radhakrishnan case TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND: 156*a9e0260cSVignesh Radhakrishnan /* 157*a9e0260cSVignesh Radhakrishnan * System suspend fake mode is set if we are on VDK and we make 158*a9e0260cSVignesh Radhakrishnan * a debug SIP call. This mode ensures that we excercise debug 159*a9e0260cSVignesh Radhakrishnan * path instead of the regular code path to suit the pre-silicon 160*a9e0260cSVignesh Radhakrishnan * platform needs. These include replacing the call to WFI by 161*a9e0260cSVignesh Radhakrishnan * a warm reset request. 162*a9e0260cSVignesh Radhakrishnan */ 163*a9e0260cSVignesh Radhakrishnan if (tegra_platform_is_emulation() != 0U) { 164*a9e0260cSVignesh Radhakrishnan 165*a9e0260cSVignesh Radhakrishnan tegra_fake_system_suspend = 1; 166*a9e0260cSVignesh Radhakrishnan SMC_RET1(handle, 0); 167*a9e0260cSVignesh Radhakrishnan } 168*a9e0260cSVignesh Radhakrishnan 169*a9e0260cSVignesh Radhakrishnan /* 170*a9e0260cSVignesh Radhakrishnan * We return to the external world as if this SIP is not 171*a9e0260cSVignesh Radhakrishnan * implemented in case, we are not running on VDK. 172*a9e0260cSVignesh Radhakrishnan */ 173*a9e0260cSVignesh Radhakrishnan break; 174*a9e0260cSVignesh Radhakrishnan 175d288ab24SVarun Wadekar default: 176d288ab24SVarun Wadekar ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 177d288ab24SVarun Wadekar break; 178d288ab24SVarun Wadekar } 179d288ab24SVarun Wadekar 180d288ab24SVarun Wadekar SMC_RET1(handle, SMC_UNK); 181d288ab24SVarun Wadekar } 182d288ab24SVarun Wadekar 183d288ab24SVarun Wadekar /* Define a runtime service descriptor for fast SMC calls */ 184d288ab24SVarun Wadekar DECLARE_RT_SVC( 185d288ab24SVarun Wadekar tegra_sip_fast, 186d288ab24SVarun Wadekar 187d288ab24SVarun Wadekar OEN_SIP_START, 188d288ab24SVarun Wadekar OEN_SIP_END, 189d288ab24SVarun Wadekar SMC_TYPE_FAST, 190d288ab24SVarun Wadekar NULL, 191d288ab24SVarun Wadekar tegra_sip_handler 192d288ab24SVarun Wadekar ); 193