1d288ab24SVarun Wadekar /* 2d288ab24SVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3d288ab24SVarun Wadekar * 4d288ab24SVarun Wadekar * Redistribution and use in source and binary forms, with or without 5d288ab24SVarun Wadekar * modification, are permitted provided that the following conditions are met: 6d288ab24SVarun Wadekar * 7d288ab24SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 8d288ab24SVarun Wadekar * list of conditions and the following disclaimer. 9d288ab24SVarun Wadekar * 10d288ab24SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 11d288ab24SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 12d288ab24SVarun Wadekar * and/or other materials provided with the distribution. 13d288ab24SVarun Wadekar * 14d288ab24SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 15d288ab24SVarun Wadekar * to endorse or promote products derived from this software without specific 16d288ab24SVarun Wadekar * prior written permission. 17d288ab24SVarun Wadekar * 18d288ab24SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19d288ab24SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20d288ab24SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21d288ab24SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22d288ab24SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23d288ab24SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24d288ab24SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25d288ab24SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26d288ab24SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27d288ab24SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28d288ab24SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 29d288ab24SVarun Wadekar */ 30d288ab24SVarun Wadekar 31d288ab24SVarun Wadekar #include <arch.h> 32d288ab24SVarun Wadekar #include <arch_helpers.h> 33d288ab24SVarun Wadekar #include <assert.h> 34d288ab24SVarun Wadekar #include <bl_common.h> 35d288ab24SVarun Wadekar #include <debug.h> 36d288ab24SVarun Wadekar #include <errno.h> 37d288ab24SVarun Wadekar #include <memctrl.h> 38d288ab24SVarun Wadekar #include <runtime_svc.h> 39d288ab24SVarun Wadekar #include <tegra_private.h> 40d288ab24SVarun Wadekar 41d288ab24SVarun Wadekar /******************************************************************************* 42d288ab24SVarun Wadekar * Common Tegra SiP SMCs 43d288ab24SVarun Wadekar ******************************************************************************/ 44d288ab24SVarun Wadekar #define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003 45*78e2bd10SVarun Wadekar #define TEGRA_SIP_FIQ_NS_ENTRYPOINT 0x82000005 46*78e2bd10SVarun Wadekar #define TEGRA_SIP_FIQ_NS_GET_CONTEXT 0x82000006 47d288ab24SVarun Wadekar 48d288ab24SVarun Wadekar /******************************************************************************* 49d288ab24SVarun Wadekar * SoC specific SiP handler 50d288ab24SVarun Wadekar ******************************************************************************/ 51d288ab24SVarun Wadekar #pragma weak plat_sip_handler 52d288ab24SVarun Wadekar int plat_sip_handler(uint32_t smc_fid, 53d288ab24SVarun Wadekar uint64_t x1, 54d288ab24SVarun Wadekar uint64_t x2, 55d288ab24SVarun Wadekar uint64_t x3, 56d288ab24SVarun Wadekar uint64_t x4, 57d288ab24SVarun Wadekar void *cookie, 58d288ab24SVarun Wadekar void *handle, 59d288ab24SVarun Wadekar uint64_t flags) 60d288ab24SVarun Wadekar { 61d288ab24SVarun Wadekar return -ENOTSUP; 62d288ab24SVarun Wadekar } 63d288ab24SVarun Wadekar 64d288ab24SVarun Wadekar /******************************************************************************* 652d05f810SWayne Lin * This function is responsible for handling all SiP calls 66d288ab24SVarun Wadekar ******************************************************************************/ 67d288ab24SVarun Wadekar uint64_t tegra_sip_handler(uint32_t smc_fid, 68d288ab24SVarun Wadekar uint64_t x1, 69d288ab24SVarun Wadekar uint64_t x2, 70d288ab24SVarun Wadekar uint64_t x3, 71d288ab24SVarun Wadekar uint64_t x4, 72d288ab24SVarun Wadekar void *cookie, 73d288ab24SVarun Wadekar void *handle, 74d288ab24SVarun Wadekar uint64_t flags) 75d288ab24SVarun Wadekar { 76d288ab24SVarun Wadekar int err; 77d288ab24SVarun Wadekar 78d288ab24SVarun Wadekar /* Check if this is a SoC specific SiP */ 79d288ab24SVarun Wadekar err = plat_sip_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); 80d288ab24SVarun Wadekar if (err == 0) 81d288ab24SVarun Wadekar SMC_RET1(handle, err); 82d288ab24SVarun Wadekar 83d288ab24SVarun Wadekar switch (smc_fid) { 84d288ab24SVarun Wadekar 85d288ab24SVarun Wadekar case TEGRA_SIP_NEW_VIDEOMEM_REGION: 86d288ab24SVarun Wadekar 87d288ab24SVarun Wadekar /* clean up the high bits */ 88d288ab24SVarun Wadekar x1 = (uint32_t)x1; 89d288ab24SVarun Wadekar x2 = (uint32_t)x2; 90d288ab24SVarun Wadekar 91d288ab24SVarun Wadekar /* 92d288ab24SVarun Wadekar * Check if Video Memory overlaps TZDRAM (contains bl31/bl32) 93d288ab24SVarun Wadekar * or falls outside of the valid DRAM range 94d288ab24SVarun Wadekar */ 95d288ab24SVarun Wadekar err = bl31_check_ns_address(x1, x2); 96d288ab24SVarun Wadekar if (err) 97d288ab24SVarun Wadekar SMC_RET1(handle, err); 98d288ab24SVarun Wadekar 99d288ab24SVarun Wadekar /* 100d288ab24SVarun Wadekar * Check if Video Memory is aligned to 1MB. 101d288ab24SVarun Wadekar */ 102d288ab24SVarun Wadekar if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) { 103d288ab24SVarun Wadekar ERROR("Unaligned Video Memory base address!\n"); 104d288ab24SVarun Wadekar SMC_RET1(handle, -ENOTSUP); 105d288ab24SVarun Wadekar } 106d288ab24SVarun Wadekar 107d288ab24SVarun Wadekar /* new video memory carveout settings */ 108d288ab24SVarun Wadekar tegra_memctrl_videomem_setup(x1, x2); 109d288ab24SVarun Wadekar 110d288ab24SVarun Wadekar SMC_RET1(handle, 0); 111d288ab24SVarun Wadekar break; 112d288ab24SVarun Wadekar 113*78e2bd10SVarun Wadekar /* 114*78e2bd10SVarun Wadekar * The NS world registers the address of its handler to be 115*78e2bd10SVarun Wadekar * used for processing the FIQ. This is normally used by the 116*78e2bd10SVarun Wadekar * NS FIQ debugger driver to detect system hangs by programming 117*78e2bd10SVarun Wadekar * a watchdog timer to fire a FIQ interrupt. 118*78e2bd10SVarun Wadekar */ 119*78e2bd10SVarun Wadekar case TEGRA_SIP_FIQ_NS_ENTRYPOINT: 120*78e2bd10SVarun Wadekar 121*78e2bd10SVarun Wadekar if (!x1) 122*78e2bd10SVarun Wadekar SMC_RET1(handle, SMC_UNK); 123*78e2bd10SVarun Wadekar 124*78e2bd10SVarun Wadekar /* 125*78e2bd10SVarun Wadekar * TODO: Check if x1 contains a valid DRAM address 126*78e2bd10SVarun Wadekar */ 127*78e2bd10SVarun Wadekar 128*78e2bd10SVarun Wadekar /* store the NS world's entrypoint */ 129*78e2bd10SVarun Wadekar tegra_fiq_set_ns_entrypoint(x1); 130*78e2bd10SVarun Wadekar 131*78e2bd10SVarun Wadekar SMC_RET1(handle, 0); 132*78e2bd10SVarun Wadekar break; 133*78e2bd10SVarun Wadekar 134*78e2bd10SVarun Wadekar /* 135*78e2bd10SVarun Wadekar * The NS world's FIQ handler issues this SMC to get the NS EL1/EL0 136*78e2bd10SVarun Wadekar * CPU context when the FIQ interrupt was triggered. This allows the 137*78e2bd10SVarun Wadekar * NS world to understand the CPU state when the watchdog interrupt 138*78e2bd10SVarun Wadekar * triggered. 139*78e2bd10SVarun Wadekar */ 140*78e2bd10SVarun Wadekar case TEGRA_SIP_FIQ_NS_GET_CONTEXT: 141*78e2bd10SVarun Wadekar 142*78e2bd10SVarun Wadekar /* retrieve context registers when FIQ triggered */ 143*78e2bd10SVarun Wadekar tegra_fiq_get_intr_context(); 144*78e2bd10SVarun Wadekar 145*78e2bd10SVarun Wadekar SMC_RET0(handle); 146*78e2bd10SVarun Wadekar break; 147*78e2bd10SVarun Wadekar 148d288ab24SVarun Wadekar default: 149d288ab24SVarun Wadekar ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 150d288ab24SVarun Wadekar break; 151d288ab24SVarun Wadekar } 152d288ab24SVarun Wadekar 153d288ab24SVarun Wadekar SMC_RET1(handle, SMC_UNK); 154d288ab24SVarun Wadekar } 155d288ab24SVarun Wadekar 156d288ab24SVarun Wadekar /* Define a runtime service descriptor for fast SMC calls */ 157d288ab24SVarun Wadekar DECLARE_RT_SVC( 158d288ab24SVarun Wadekar tegra_sip_fast, 159d288ab24SVarun Wadekar 160d288ab24SVarun Wadekar OEN_SIP_START, 161d288ab24SVarun Wadekar OEN_SIP_END, 162d288ab24SVarun Wadekar SMC_TYPE_FAST, 163d288ab24SVarun Wadekar NULL, 164d288ab24SVarun Wadekar tegra_sip_handler 165d288ab24SVarun Wadekar ); 166