1d288ab24SVarun Wadekar /* 2a9e0260cSVignesh Radhakrishnan * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3d288ab24SVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5d288ab24SVarun Wadekar */ 6d288ab24SVarun Wadekar 7d288ab24SVarun Wadekar #include <arch.h> 8d288ab24SVarun Wadekar #include <arch_helpers.h> 9d288ab24SVarun Wadekar #include <assert.h> 10d288ab24SVarun Wadekar #include <bl_common.h> 11d288ab24SVarun Wadekar #include <debug.h> 12d288ab24SVarun Wadekar #include <errno.h> 13d288ab24SVarun Wadekar #include <memctrl.h> 14f5f64e4dSVarun Wadekar #include <mmio.h> 15d288ab24SVarun Wadekar #include <runtime_svc.h> 16a9e0260cSVignesh Radhakrishnan #include <tegra_platform.h> 17ee1ebbd1SIsla Mitchell #include <tegra_private.h> 18d288ab24SVarun Wadekar 19d288ab24SVarun Wadekar /******************************************************************************* 20d288ab24SVarun Wadekar * Common Tegra SiP SMCs 21d288ab24SVarun Wadekar ******************************************************************************/ 22d288ab24SVarun Wadekar #define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003 2378e2bd10SVarun Wadekar #define TEGRA_SIP_FIQ_NS_ENTRYPOINT 0x82000005 2478e2bd10SVarun Wadekar #define TEGRA_SIP_FIQ_NS_GET_CONTEXT 0x82000006 25a9e0260cSVignesh Radhakrishnan #define TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND 0xC2000007 26a9e0260cSVignesh Radhakrishnan 27a9e0260cSVignesh Radhakrishnan /******************************************************************************* 28a9e0260cSVignesh Radhakrishnan * Fake system suspend mode control var 29a9e0260cSVignesh Radhakrishnan ******************************************************************************/ 30a9e0260cSVignesh Radhakrishnan extern uint8_t tegra_fake_system_suspend; 31a9e0260cSVignesh Radhakrishnan 32d288ab24SVarun Wadekar 33d288ab24SVarun Wadekar /******************************************************************************* 34d288ab24SVarun Wadekar * SoC specific SiP handler 35d288ab24SVarun Wadekar ******************************************************************************/ 36d288ab24SVarun Wadekar #pragma weak plat_sip_handler 37d288ab24SVarun Wadekar int plat_sip_handler(uint32_t smc_fid, 38d288ab24SVarun Wadekar uint64_t x1, 39d288ab24SVarun Wadekar uint64_t x2, 40d288ab24SVarun Wadekar uint64_t x3, 41d288ab24SVarun Wadekar uint64_t x4, 42d288ab24SVarun Wadekar void *cookie, 43d288ab24SVarun Wadekar void *handle, 44d288ab24SVarun Wadekar uint64_t flags) 45d288ab24SVarun Wadekar { 46d288ab24SVarun Wadekar return -ENOTSUP; 47d288ab24SVarun Wadekar } 48d288ab24SVarun Wadekar 49d288ab24SVarun Wadekar /******************************************************************************* 502d05f810SWayne Lin * This function is responsible for handling all SiP calls 51d288ab24SVarun Wadekar ******************************************************************************/ 52*57d1e5faSMasahiro Yamada uintptr_t tegra_sip_handler(uint32_t smc_fid, 53*57d1e5faSMasahiro Yamada u_register_t x1, 54*57d1e5faSMasahiro Yamada u_register_t x2, 55*57d1e5faSMasahiro Yamada u_register_t x3, 56*57d1e5faSMasahiro Yamada u_register_t x4, 57d288ab24SVarun Wadekar void *cookie, 58d288ab24SVarun Wadekar void *handle, 59*57d1e5faSMasahiro Yamada u_register_t flags) 60d288ab24SVarun Wadekar { 61f5f64e4dSVarun Wadekar uint32_t regval; 62d288ab24SVarun Wadekar int err; 63d288ab24SVarun Wadekar 64d288ab24SVarun Wadekar /* Check if this is a SoC specific SiP */ 65d288ab24SVarun Wadekar err = plat_sip_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); 66d288ab24SVarun Wadekar if (err == 0) 67c76c1b71SVarun Wadekar SMC_RET1(handle, (uint64_t)err); 68d288ab24SVarun Wadekar 69d288ab24SVarun Wadekar switch (smc_fid) { 70d288ab24SVarun Wadekar 71d288ab24SVarun Wadekar case TEGRA_SIP_NEW_VIDEOMEM_REGION: 72d288ab24SVarun Wadekar 73d288ab24SVarun Wadekar /* clean up the high bits */ 74d288ab24SVarun Wadekar x2 = (uint32_t)x2; 75d288ab24SVarun Wadekar 76d288ab24SVarun Wadekar /* 77d288ab24SVarun Wadekar * Check if Video Memory overlaps TZDRAM (contains bl31/bl32) 78d288ab24SVarun Wadekar * or falls outside of the valid DRAM range 79d288ab24SVarun Wadekar */ 80d288ab24SVarun Wadekar err = bl31_check_ns_address(x1, x2); 81d288ab24SVarun Wadekar if (err) 82d288ab24SVarun Wadekar SMC_RET1(handle, err); 83d288ab24SVarun Wadekar 84d288ab24SVarun Wadekar /* 85d288ab24SVarun Wadekar * Check if Video Memory is aligned to 1MB. 86d288ab24SVarun Wadekar */ 87d288ab24SVarun Wadekar if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) { 88d288ab24SVarun Wadekar ERROR("Unaligned Video Memory base address!\n"); 89d288ab24SVarun Wadekar SMC_RET1(handle, -ENOTSUP); 90d288ab24SVarun Wadekar } 91d288ab24SVarun Wadekar 92f5f64e4dSVarun Wadekar /* 93f5f64e4dSVarun Wadekar * The GPU is the user of the Video Memory region. In order to 94f5f64e4dSVarun Wadekar * transition to the new memory region smoothly, we program the 95f5f64e4dSVarun Wadekar * new base/size ONLY if the GPU is in reset mode. 96f5f64e4dSVarun Wadekar */ 97f5f64e4dSVarun Wadekar regval = mmio_read_32(TEGRA_CAR_RESET_BASE + 98f5f64e4dSVarun Wadekar TEGRA_GPU_RESET_REG_OFFSET); 99f5f64e4dSVarun Wadekar if ((regval & GPU_RESET_BIT) == 0U) { 100f5f64e4dSVarun Wadekar ERROR("GPU not in reset! Video Memory setup failed\n"); 101f5f64e4dSVarun Wadekar SMC_RET1(handle, -ENOTSUP); 102f5f64e4dSVarun Wadekar } 103f5f64e4dSVarun Wadekar 104d288ab24SVarun Wadekar /* new video memory carveout settings */ 105d288ab24SVarun Wadekar tegra_memctrl_videomem_setup(x1, x2); 106d288ab24SVarun Wadekar 107d288ab24SVarun Wadekar SMC_RET1(handle, 0); 108d288ab24SVarun Wadekar break; 109d288ab24SVarun Wadekar 11078e2bd10SVarun Wadekar /* 11178e2bd10SVarun Wadekar * The NS world registers the address of its handler to be 11278e2bd10SVarun Wadekar * used for processing the FIQ. This is normally used by the 11378e2bd10SVarun Wadekar * NS FIQ debugger driver to detect system hangs by programming 11478e2bd10SVarun Wadekar * a watchdog timer to fire a FIQ interrupt. 11578e2bd10SVarun Wadekar */ 11678e2bd10SVarun Wadekar case TEGRA_SIP_FIQ_NS_ENTRYPOINT: 11778e2bd10SVarun Wadekar 11878e2bd10SVarun Wadekar if (!x1) 11978e2bd10SVarun Wadekar SMC_RET1(handle, SMC_UNK); 12078e2bd10SVarun Wadekar 12178e2bd10SVarun Wadekar /* 12278e2bd10SVarun Wadekar * TODO: Check if x1 contains a valid DRAM address 12378e2bd10SVarun Wadekar */ 12478e2bd10SVarun Wadekar 12578e2bd10SVarun Wadekar /* store the NS world's entrypoint */ 12678e2bd10SVarun Wadekar tegra_fiq_set_ns_entrypoint(x1); 12778e2bd10SVarun Wadekar 12878e2bd10SVarun Wadekar SMC_RET1(handle, 0); 12978e2bd10SVarun Wadekar break; 13078e2bd10SVarun Wadekar 13178e2bd10SVarun Wadekar /* 13278e2bd10SVarun Wadekar * The NS world's FIQ handler issues this SMC to get the NS EL1/EL0 13378e2bd10SVarun Wadekar * CPU context when the FIQ interrupt was triggered. This allows the 13478e2bd10SVarun Wadekar * NS world to understand the CPU state when the watchdog interrupt 13578e2bd10SVarun Wadekar * triggered. 13678e2bd10SVarun Wadekar */ 13778e2bd10SVarun Wadekar case TEGRA_SIP_FIQ_NS_GET_CONTEXT: 13878e2bd10SVarun Wadekar 13978e2bd10SVarun Wadekar /* retrieve context registers when FIQ triggered */ 14078e2bd10SVarun Wadekar tegra_fiq_get_intr_context(); 14178e2bd10SVarun Wadekar 14278e2bd10SVarun Wadekar SMC_RET0(handle); 14378e2bd10SVarun Wadekar break; 14478e2bd10SVarun Wadekar 145a9e0260cSVignesh Radhakrishnan case TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND: 146a9e0260cSVignesh Radhakrishnan /* 147a9e0260cSVignesh Radhakrishnan * System suspend fake mode is set if we are on VDK and we make 148a9e0260cSVignesh Radhakrishnan * a debug SIP call. This mode ensures that we excercise debug 149a9e0260cSVignesh Radhakrishnan * path instead of the regular code path to suit the pre-silicon 150a9e0260cSVignesh Radhakrishnan * platform needs. These include replacing the call to WFI by 151a9e0260cSVignesh Radhakrishnan * a warm reset request. 152a9e0260cSVignesh Radhakrishnan */ 153a9e0260cSVignesh Radhakrishnan if (tegra_platform_is_emulation() != 0U) { 154a9e0260cSVignesh Radhakrishnan 155a9e0260cSVignesh Radhakrishnan tegra_fake_system_suspend = 1; 156a9e0260cSVignesh Radhakrishnan SMC_RET1(handle, 0); 157a9e0260cSVignesh Radhakrishnan } 158a9e0260cSVignesh Radhakrishnan 159a9e0260cSVignesh Radhakrishnan /* 160a9e0260cSVignesh Radhakrishnan * We return to the external world as if this SIP is not 161a9e0260cSVignesh Radhakrishnan * implemented in case, we are not running on VDK. 162a9e0260cSVignesh Radhakrishnan */ 163a9e0260cSVignesh Radhakrishnan break; 164a9e0260cSVignesh Radhakrishnan 165d288ab24SVarun Wadekar default: 166d288ab24SVarun Wadekar ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 167d288ab24SVarun Wadekar break; 168d288ab24SVarun Wadekar } 169d288ab24SVarun Wadekar 170d288ab24SVarun Wadekar SMC_RET1(handle, SMC_UNK); 171d288ab24SVarun Wadekar } 172d288ab24SVarun Wadekar 173d288ab24SVarun Wadekar /* Define a runtime service descriptor for fast SMC calls */ 174d288ab24SVarun Wadekar DECLARE_RT_SVC( 175d288ab24SVarun Wadekar tegra_sip_fast, 176d288ab24SVarun Wadekar 177d288ab24SVarun Wadekar OEN_SIP_START, 178d288ab24SVarun Wadekar OEN_SIP_END, 179d288ab24SVarun Wadekar SMC_TYPE_FAST, 180d288ab24SVarun Wadekar NULL, 181d288ab24SVarun Wadekar tegra_sip_handler 182d288ab24SVarun Wadekar ); 183