1d288ab24SVarun Wadekar /* 2d288ab24SVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3d288ab24SVarun Wadekar * 4d288ab24SVarun Wadekar * Redistribution and use in source and binary forms, with or without 5d288ab24SVarun Wadekar * modification, are permitted provided that the following conditions are met: 6d288ab24SVarun Wadekar * 7d288ab24SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 8d288ab24SVarun Wadekar * list of conditions and the following disclaimer. 9d288ab24SVarun Wadekar * 10d288ab24SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 11d288ab24SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 12d288ab24SVarun Wadekar * and/or other materials provided with the distribution. 13d288ab24SVarun Wadekar * 14d288ab24SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 15d288ab24SVarun Wadekar * to endorse or promote products derived from this software without specific 16d288ab24SVarun Wadekar * prior written permission. 17d288ab24SVarun Wadekar * 18d288ab24SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19d288ab24SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20d288ab24SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21d288ab24SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22d288ab24SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23d288ab24SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24d288ab24SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25d288ab24SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26d288ab24SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27d288ab24SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28d288ab24SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 29d288ab24SVarun Wadekar */ 30d288ab24SVarun Wadekar 31d288ab24SVarun Wadekar #include <arch.h> 32d288ab24SVarun Wadekar #include <arch_helpers.h> 33d288ab24SVarun Wadekar #include <assert.h> 34d288ab24SVarun Wadekar #include <bl_common.h> 35d288ab24SVarun Wadekar #include <debug.h> 36d288ab24SVarun Wadekar #include <errno.h> 37d288ab24SVarun Wadekar #include <memctrl.h> 38d288ab24SVarun Wadekar #include <runtime_svc.h> 39d288ab24SVarun Wadekar #include <tegra_private.h> 40d288ab24SVarun Wadekar 41d288ab24SVarun Wadekar /******************************************************************************* 42d288ab24SVarun Wadekar * Common Tegra SiP SMCs 43d288ab24SVarun Wadekar ******************************************************************************/ 44d288ab24SVarun Wadekar #define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003 45d288ab24SVarun Wadekar 46d288ab24SVarun Wadekar /******************************************************************************* 47d288ab24SVarun Wadekar * SoC specific SiP handler 48d288ab24SVarun Wadekar ******************************************************************************/ 49d288ab24SVarun Wadekar #pragma weak plat_sip_handler 50d288ab24SVarun Wadekar int plat_sip_handler(uint32_t smc_fid, 51d288ab24SVarun Wadekar uint64_t x1, 52d288ab24SVarun Wadekar uint64_t x2, 53d288ab24SVarun Wadekar uint64_t x3, 54d288ab24SVarun Wadekar uint64_t x4, 55d288ab24SVarun Wadekar void *cookie, 56d288ab24SVarun Wadekar void *handle, 57d288ab24SVarun Wadekar uint64_t flags) 58d288ab24SVarun Wadekar { 59d288ab24SVarun Wadekar return -ENOTSUP; 60d288ab24SVarun Wadekar } 61d288ab24SVarun Wadekar 62d288ab24SVarun Wadekar /******************************************************************************* 63*2d05f810SWayne Lin * This function is responsible for handling all SiP calls 64d288ab24SVarun Wadekar ******************************************************************************/ 65d288ab24SVarun Wadekar uint64_t tegra_sip_handler(uint32_t smc_fid, 66d288ab24SVarun Wadekar uint64_t x1, 67d288ab24SVarun Wadekar uint64_t x2, 68d288ab24SVarun Wadekar uint64_t x3, 69d288ab24SVarun Wadekar uint64_t x4, 70d288ab24SVarun Wadekar void *cookie, 71d288ab24SVarun Wadekar void *handle, 72d288ab24SVarun Wadekar uint64_t flags) 73d288ab24SVarun Wadekar { 74d288ab24SVarun Wadekar int err; 75d288ab24SVarun Wadekar 76d288ab24SVarun Wadekar /* Check if this is a SoC specific SiP */ 77d288ab24SVarun Wadekar err = plat_sip_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); 78d288ab24SVarun Wadekar if (err == 0) 79d288ab24SVarun Wadekar SMC_RET1(handle, err); 80d288ab24SVarun Wadekar 81d288ab24SVarun Wadekar switch (smc_fid) { 82d288ab24SVarun Wadekar 83d288ab24SVarun Wadekar case TEGRA_SIP_NEW_VIDEOMEM_REGION: 84d288ab24SVarun Wadekar 85d288ab24SVarun Wadekar /* clean up the high bits */ 86d288ab24SVarun Wadekar x1 = (uint32_t)x1; 87d288ab24SVarun Wadekar x2 = (uint32_t)x2; 88d288ab24SVarun Wadekar 89d288ab24SVarun Wadekar /* 90d288ab24SVarun Wadekar * Check if Video Memory overlaps TZDRAM (contains bl31/bl32) 91d288ab24SVarun Wadekar * or falls outside of the valid DRAM range 92d288ab24SVarun Wadekar */ 93d288ab24SVarun Wadekar err = bl31_check_ns_address(x1, x2); 94d288ab24SVarun Wadekar if (err) 95d288ab24SVarun Wadekar SMC_RET1(handle, err); 96d288ab24SVarun Wadekar 97d288ab24SVarun Wadekar /* 98d288ab24SVarun Wadekar * Check if Video Memory is aligned to 1MB. 99d288ab24SVarun Wadekar */ 100d288ab24SVarun Wadekar if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) { 101d288ab24SVarun Wadekar ERROR("Unaligned Video Memory base address!\n"); 102d288ab24SVarun Wadekar SMC_RET1(handle, -ENOTSUP); 103d288ab24SVarun Wadekar } 104d288ab24SVarun Wadekar 105d288ab24SVarun Wadekar /* new video memory carveout settings */ 106d288ab24SVarun Wadekar tegra_memctrl_videomem_setup(x1, x2); 107d288ab24SVarun Wadekar 108d288ab24SVarun Wadekar SMC_RET1(handle, 0); 109d288ab24SVarun Wadekar break; 110d288ab24SVarun Wadekar 111d288ab24SVarun Wadekar default: 112d288ab24SVarun Wadekar ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 113d288ab24SVarun Wadekar break; 114d288ab24SVarun Wadekar } 115d288ab24SVarun Wadekar 116d288ab24SVarun Wadekar SMC_RET1(handle, SMC_UNK); 117d288ab24SVarun Wadekar } 118d288ab24SVarun Wadekar 119d288ab24SVarun Wadekar /* Define a runtime service descriptor for fast SMC calls */ 120d288ab24SVarun Wadekar DECLARE_RT_SVC( 121d288ab24SVarun Wadekar tegra_sip_fast, 122d288ab24SVarun Wadekar 123d288ab24SVarun Wadekar OEN_SIP_START, 124d288ab24SVarun Wadekar OEN_SIP_END, 125d288ab24SVarun Wadekar SMC_TYPE_FAST, 126d288ab24SVarun Wadekar NULL, 127d288ab24SVarun Wadekar tegra_sip_handler 128d288ab24SVarun Wadekar ); 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