1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <bl_common.h> 34 #include <context.h> 35 #include <context_mgmt.h> 36 #include <debug.h> 37 #include <memctrl.h> 38 #include <mmio.h> 39 #include <platform.h> 40 #include <platform_def.h> 41 #include <pmc.h> 42 #include <psci.h> 43 #include <tegra_def.h> 44 #include <tegra_private.h> 45 46 extern uint64_t tegra_bl31_phys_base; 47 extern uint64_t tegra_sec_entry_point; 48 49 /* 50 * The following platform setup functions are weakly defined. They 51 * provide typical implementations that will be overridden by a SoC. 52 */ 53 #pragma weak tegra_soc_pwr_domain_suspend 54 #pragma weak tegra_soc_pwr_domain_on 55 #pragma weak tegra_soc_pwr_domain_off 56 #pragma weak tegra_soc_pwr_domain_on_finish 57 #pragma weak tegra_soc_prepare_system_reset 58 #pragma weak tegra_soc_prepare_system_off 59 60 int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) 61 { 62 return PSCI_E_NOT_SUPPORTED; 63 } 64 65 int tegra_soc_pwr_domain_on(u_register_t mpidr) 66 { 67 return PSCI_E_SUCCESS; 68 } 69 70 int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) 71 { 72 return PSCI_E_SUCCESS; 73 } 74 75 int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) 76 { 77 return PSCI_E_SUCCESS; 78 } 79 80 int tegra_soc_prepare_system_reset(void) 81 { 82 return PSCI_E_SUCCESS; 83 } 84 85 __dead2 void tegra_soc_prepare_system_off(void) 86 { 87 ERROR("Tegra System Off: operation not handled.\n"); 88 panic(); 89 } 90 91 /******************************************************************************* 92 * This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND` 93 * call to get the `power_state` parameter. This allows the platform to encode 94 * the appropriate State-ID field within the `power_state` parameter which can 95 * be utilized in `pwr_domain_suspend()` to suspend to system affinity level. 96 ******************************************************************************/ 97 void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state) 98 { 99 /* lower affinities use PLAT_MAX_OFF_STATE */ 100 for (int i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) 101 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 102 103 /* max affinity uses system suspend state id */ 104 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PSTATE_ID_SOC_POWERDN; 105 } 106 107 /******************************************************************************* 108 * Handler called when an affinity instance is about to enter standby. 109 ******************************************************************************/ 110 void tegra_cpu_standby(plat_local_state_t cpu_state) 111 { 112 /* 113 * Enter standby state 114 * dsb is good practice before using wfi to enter low power states 115 */ 116 dsb(); 117 wfi(); 118 } 119 120 /******************************************************************************* 121 * Handler called when an affinity instance is about to be turned on. The 122 * level and mpidr determine the affinity instance. 123 ******************************************************************************/ 124 int tegra_pwr_domain_on(u_register_t mpidr) 125 { 126 return tegra_soc_pwr_domain_on(mpidr); 127 } 128 129 /******************************************************************************* 130 * Handler called when a power domain is about to be turned off. The 131 * target_state encodes the power state that each level should transition to. 132 ******************************************************************************/ 133 void tegra_pwr_domain_off(const psci_power_state_t *target_state) 134 { 135 tegra_soc_pwr_domain_off(target_state); 136 } 137 138 /******************************************************************************* 139 * Handler called when called when a power domain is about to be suspended. The 140 * target_state encodes the power state that each level should transition to. 141 ******************************************************************************/ 142 void tegra_pwr_domain_suspend(const psci_power_state_t *target_state) 143 { 144 tegra_soc_pwr_domain_suspend(target_state); 145 146 /* disable GICC */ 147 tegra_gic_cpuif_deactivate(); 148 } 149 150 /******************************************************************************* 151 * Handler called when a power domain has just been powered on after 152 * being turned off earlier. The target_state encodes the low power state that 153 * each level has woken up from. 154 ******************************************************************************/ 155 void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state) 156 { 157 plat_params_from_bl2_t *plat_params; 158 159 /* 160 * Initialize the GIC cpu and distributor interfaces 161 */ 162 tegra_gic_setup(); 163 164 /* 165 * Check if we are exiting from deep sleep. 166 */ 167 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == 168 PSTATE_ID_SOC_POWERDN) { 169 170 /* 171 * Lock scratch registers which hold the CPU vectors. 172 */ 173 tegra_pmc_lock_cpu_vectors(); 174 175 /* 176 * SMMU configuration. 177 */ 178 tegra_memctrl_setup(); 179 180 /* 181 * Security configuration to allow DRAM/device access. 182 */ 183 plat_params = bl31_get_plat_params(); 184 tegra_memctrl_tzdram_setup(plat_params->tzdram_base, 185 plat_params->tzdram_size); 186 } 187 188 /* 189 * Reset hardware settings. 190 */ 191 tegra_soc_pwr_domain_on_finish(target_state); 192 } 193 194 /******************************************************************************* 195 * Handler called when a power domain has just been powered on after 196 * having been suspended earlier. The target_state encodes the low power state 197 * that each level has woken up from. 198 ******************************************************************************/ 199 void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 200 { 201 tegra_pwr_domain_on_finish(target_state); 202 } 203 204 /******************************************************************************* 205 * Handler called when the system wants to be powered off 206 ******************************************************************************/ 207 __dead2 void tegra_system_off(void) 208 { 209 INFO("Powering down system...\n"); 210 211 tegra_soc_prepare_system_off(); 212 } 213 214 /******************************************************************************* 215 * Handler called when the system wants to be restarted. 216 ******************************************************************************/ 217 __dead2 void tegra_system_reset(void) 218 { 219 INFO("Restarting system...\n"); 220 221 /* per-SoC system reset handler */ 222 tegra_soc_prepare_system_reset(); 223 224 /* 225 * Program the PMC in order to restart the system. 226 */ 227 tegra_pmc_system_reset(); 228 } 229 230 /******************************************************************************* 231 * Handler called to check the validity of the power state parameter. 232 ******************************************************************************/ 233 int32_t tegra_validate_power_state(unsigned int power_state, 234 psci_power_state_t *req_state) 235 { 236 int pwr_lvl = psci_get_pstate_pwrlvl(power_state); 237 238 assert(req_state); 239 240 if (pwr_lvl > PLAT_MAX_PWR_LVL) 241 return PSCI_E_INVALID_PARAMS; 242 243 return tegra_soc_validate_power_state(power_state, req_state); 244 } 245 246 /******************************************************************************* 247 * Platform handler called to check the validity of the non secure entrypoint. 248 ******************************************************************************/ 249 int tegra_validate_ns_entrypoint(uintptr_t entrypoint) 250 { 251 /* 252 * Check if the non secure entrypoint lies within the non 253 * secure DRAM. 254 */ 255 if ((entrypoint >= TEGRA_DRAM_BASE) && (entrypoint <= TEGRA_DRAM_END)) 256 return PSCI_E_SUCCESS; 257 258 return PSCI_E_INVALID_ADDRESS; 259 } 260 261 /******************************************************************************* 262 * Export the platform handlers to enable psci to invoke them 263 ******************************************************************************/ 264 static const plat_psci_ops_t tegra_plat_psci_ops = { 265 .cpu_standby = tegra_cpu_standby, 266 .pwr_domain_on = tegra_pwr_domain_on, 267 .pwr_domain_off = tegra_pwr_domain_off, 268 .pwr_domain_suspend = tegra_pwr_domain_suspend, 269 .pwr_domain_on_finish = tegra_pwr_domain_on_finish, 270 .pwr_domain_suspend_finish = tegra_pwr_domain_suspend_finish, 271 .system_off = tegra_system_off, 272 .system_reset = tegra_system_reset, 273 .validate_power_state = tegra_validate_power_state, 274 .validate_ns_entrypoint = tegra_validate_ns_entrypoint, 275 .get_sys_suspend_power_state = tegra_get_sys_suspend_power_state, 276 }; 277 278 /******************************************************************************* 279 * Export the platform specific power ops and initialize Power Controller 280 ******************************************************************************/ 281 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 282 const plat_psci_ops_t **psci_ops) 283 { 284 psci_power_state_t target_state = { { PSCI_LOCAL_STATE_RUN } }; 285 286 /* 287 * Flush entrypoint variable to PoC since it will be 288 * accessed after a reset with the caches turned off. 289 */ 290 tegra_sec_entry_point = sec_entrypoint; 291 flush_dcache_range((uint64_t)&tegra_sec_entry_point, sizeof(uint64_t)); 292 293 /* 294 * Reset hardware settings. 295 */ 296 tegra_soc_pwr_domain_on_finish(&target_state); 297 298 /* 299 * Initialize PSCI ops struct 300 */ 301 *psci_ops = &tegra_plat_psci_ops; 302 303 return 0; 304 } 305