1 /* 2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <lib/mmio.h> 10 #include <tegra_def.h> 11 #include <tegra_platform.h> 12 #include <tegra_private.h> 13 14 /******************************************************************************* 15 * Tegra platforms 16 ******************************************************************************/ 17 typedef enum tegra_platform { 18 TEGRA_PLATFORM_SILICON = 0, 19 TEGRA_PLATFORM_QT, 20 TEGRA_PLATFORM_FPGA, 21 TEGRA_PLATFORM_EMULATION, 22 TEGRA_PLATFORM_LINSIM, 23 TEGRA_PLATFORM_UNIT_FPGA, 24 TEGRA_PLATFORM_VIRT_DEV_KIT, 25 TEGRA_PLATFORM_MAX, 26 } tegra_platform_t; 27 28 /******************************************************************************* 29 * Tegra macros defining all the SoC minor versions 30 ******************************************************************************/ 31 #define TEGRA_MINOR_QT U(0) 32 #define TEGRA_MINOR_FPGA U(1) 33 #define TEGRA_MINOR_ASIM_QT U(2) 34 #define TEGRA_MINOR_ASIM_LINSIM U(3) 35 #define TEGRA_MINOR_DSIM_ASIM_LINSIM U(4) 36 #define TEGRA_MINOR_UNIT_FPGA U(5) 37 #define TEGRA_MINOR_VIRT_DEV_KIT U(6) 38 39 /******************************************************************************* 40 * Tegra macros defining all the SoC pre_si_platform 41 ******************************************************************************/ 42 #define TEGRA_PRE_SI_QT U(1) 43 #define TEGRA_PRE_SI_FPGA U(2) 44 #define TEGRA_PRE_SI_UNIT_FPGA U(3) 45 #define TEGRA_PRE_SI_ASIM_QT U(4) 46 #define TEGRA_PRE_SI_ASIM_LINSIM U(5) 47 #define TEGRA_PRE_SI_DSIM_ASIM_LINSIM U(6) 48 #define TEGRA_PRE_SI_VDK U(8) 49 50 /* 51 * Read the chip ID value 52 */ 53 static uint32_t tegra_get_chipid(void) 54 { 55 return mmio_read_32(TEGRA_MISC_BASE + HARDWARE_REVISION_OFFSET); 56 } 57 58 /* 59 * Read the chip's major version from chip ID value 60 */ 61 uint32_t tegra_get_chipid_major(void) 62 { 63 return (tegra_get_chipid() >> MAJOR_VERSION_SHIFT) & MAJOR_VERSION_MASK; 64 } 65 66 /* 67 * Read the chip's minor version from the chip ID value 68 */ 69 uint32_t tegra_get_chipid_minor(void) 70 { 71 return (tegra_get_chipid() >> MINOR_VERSION_SHIFT) & MINOR_VERSION_MASK; 72 } 73 74 /* 75 * Read the chip's pre_si_platform valus from the chip ID value 76 */ 77 static uint32_t tegra_get_chipid_pre_si_platform(void) 78 { 79 return (tegra_get_chipid() >> PRE_SI_PLATFORM_SHIFT) & PRE_SI_PLATFORM_MASK; 80 } 81 82 bool tegra_chipid_is_t132(void) 83 { 84 uint32_t chip_id = ((tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK); 85 86 return (chip_id == (uint32_t)TEGRA_CHIPID_TEGRA13); 87 } 88 89 bool tegra_chipid_is_t186(void) 90 { 91 uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK; 92 93 return (chip_id == TEGRA_CHIPID_TEGRA18); 94 } 95 96 bool tegra_chipid_is_t210(void) 97 { 98 uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK; 99 100 return (chip_id == (uint32_t)TEGRA_CHIPID_TEGRA21); 101 } 102 103 bool tegra_chipid_is_t210_b01(void) 104 { 105 return (tegra_chipid_is_t210() && (tegra_get_chipid_major() == 0x2UL)); 106 } 107 108 /* 109 * Read the chip ID value and derive the platform 110 */ 111 static tegra_platform_t tegra_get_platform(void) 112 { 113 uint32_t major, minor, pre_si_platform; 114 tegra_platform_t ret; 115 116 /* get the major/minor chip ID values */ 117 major = tegra_get_chipid_major(); 118 minor = tegra_get_chipid_minor(); 119 pre_si_platform = tegra_get_chipid_pre_si_platform(); 120 121 if (major == 0U) { 122 /* 123 * The minor version number is used by simulation platforms 124 */ 125 switch (minor) { 126 /* 127 * Cadence's QuickTurn emulation system is a Solaris-based 128 * chip emulation system 129 */ 130 case TEGRA_MINOR_QT: 131 case TEGRA_MINOR_ASIM_QT: 132 ret = TEGRA_PLATFORM_QT; 133 break; 134 135 /* 136 * FPGAs are used during early software/hardware development 137 */ 138 case TEGRA_MINOR_FPGA: 139 ret = TEGRA_PLATFORM_FPGA; 140 break; 141 /* 142 * Linsim is a reconfigurable, clock-driven, mixed RTL/cmodel 143 * simulation framework. 144 */ 145 case TEGRA_MINOR_ASIM_LINSIM: 146 case TEGRA_MINOR_DSIM_ASIM_LINSIM: 147 ret = TEGRA_PLATFORM_LINSIM; 148 break; 149 150 /* 151 * Unit FPGAs run the actual hardware block IP on the FPGA with 152 * the other parts of the system using Linsim. 153 */ 154 case TEGRA_MINOR_UNIT_FPGA: 155 ret = TEGRA_PLATFORM_UNIT_FPGA; 156 break; 157 /* 158 * The Virtualizer Development Kit (VDK) is the standard chip 159 * development from Synopsis. 160 */ 161 case TEGRA_MINOR_VIRT_DEV_KIT: 162 ret = TEGRA_PLATFORM_VIRT_DEV_KIT; 163 break; 164 165 default: 166 ret = TEGRA_PLATFORM_MAX; 167 break; 168 } 169 170 } else if (pre_si_platform > 0U) { 171 172 switch (pre_si_platform) { 173 /* 174 * Cadence's QuickTurn emulation system is a Solaris-based 175 * chip emulation system 176 */ 177 case TEGRA_PRE_SI_QT: 178 case TEGRA_PRE_SI_ASIM_QT: 179 ret = TEGRA_PLATFORM_QT; 180 break; 181 182 /* 183 * FPGAs are used during early software/hardware development 184 */ 185 case TEGRA_PRE_SI_FPGA: 186 ret = TEGRA_PLATFORM_FPGA; 187 break; 188 /* 189 * Linsim is a reconfigurable, clock-driven, mixed RTL/cmodel 190 * simulation framework. 191 */ 192 case TEGRA_PRE_SI_ASIM_LINSIM: 193 case TEGRA_PRE_SI_DSIM_ASIM_LINSIM: 194 ret = TEGRA_PLATFORM_LINSIM; 195 break; 196 197 /* 198 * Unit FPGAs run the actual hardware block IP on the FPGA with 199 * the other parts of the system using Linsim. 200 */ 201 case TEGRA_PRE_SI_UNIT_FPGA: 202 ret = TEGRA_PLATFORM_UNIT_FPGA; 203 break; 204 /* 205 * The Virtualizer Development Kit (VDK) is the standard chip 206 * development from Synopsis. 207 */ 208 case TEGRA_PRE_SI_VDK: 209 ret = TEGRA_PLATFORM_VIRT_DEV_KIT; 210 break; 211 212 default: 213 ret = TEGRA_PLATFORM_MAX; 214 break; 215 } 216 217 } else { 218 /* Actual silicon platforms have a non-zero major version */ 219 ret = TEGRA_PLATFORM_SILICON; 220 } 221 222 return ret; 223 } 224 225 bool tegra_platform_is_silicon(void) 226 { 227 return ((tegra_get_platform() == TEGRA_PLATFORM_SILICON) ? true : false); 228 } 229 230 bool tegra_platform_is_qt(void) 231 { 232 return ((tegra_get_platform() == TEGRA_PLATFORM_QT) ? true : false); 233 } 234 235 bool tegra_platform_is_linsim(void) 236 { 237 tegra_platform_t plat = tegra_get_platform(); 238 239 return (((plat == TEGRA_PLATFORM_LINSIM) || 240 (plat == TEGRA_PLATFORM_UNIT_FPGA)) ? true : false); 241 } 242 243 bool tegra_platform_is_fpga(void) 244 { 245 return ((tegra_get_platform() == TEGRA_PLATFORM_FPGA) ? true : false); 246 } 247 248 bool tegra_platform_is_emulation(void) 249 { 250 return (tegra_get_platform() == TEGRA_PLATFORM_EMULATION); 251 } 252 253 bool tegra_platform_is_unit_fpga(void) 254 { 255 return ((tegra_get_platform() == TEGRA_PLATFORM_UNIT_FPGA) ? true : false); 256 } 257 258 bool tegra_platform_is_virt_dev_kit(void) 259 { 260 return ((tegra_get_platform() == TEGRA_PLATFORM_VIRT_DEV_KIT) ? true : false); 261 } 262