1 /* 2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <lib/mmio.h> 11 #include <tegra_def.h> 12 #include <tegra_platform.h> 13 #include <tegra_private.h> 14 15 /******************************************************************************* 16 * Tegra platforms 17 ******************************************************************************/ 18 typedef enum tegra_platform { 19 TEGRA_PLATFORM_SILICON = 0U, 20 TEGRA_PLATFORM_QT, 21 TEGRA_PLATFORM_FPGA, 22 TEGRA_PLATFORM_EMULATION, 23 TEGRA_PLATFORM_LINSIM, 24 TEGRA_PLATFORM_UNIT_FPGA, 25 TEGRA_PLATFORM_VIRT_DEV_KIT, 26 TEGRA_PLATFORM_MAX, 27 } tegra_platform_t; 28 29 /******************************************************************************* 30 * Tegra macros defining all the SoC minor versions 31 ******************************************************************************/ 32 #define TEGRA_MINOR_QT U(0) 33 #define TEGRA_MINOR_FPGA U(1) 34 #define TEGRA_MINOR_ASIM_QT U(2) 35 #define TEGRA_MINOR_ASIM_LINSIM U(3) 36 #define TEGRA_MINOR_DSIM_ASIM_LINSIM U(4) 37 #define TEGRA_MINOR_UNIT_FPGA U(5) 38 #define TEGRA_MINOR_VIRT_DEV_KIT U(6) 39 40 /******************************************************************************* 41 * Tegra macros defining all the SoC pre_si_platform 42 ******************************************************************************/ 43 #define TEGRA_PRE_SI_QT U(1) 44 #define TEGRA_PRE_SI_FPGA U(2) 45 #define TEGRA_PRE_SI_UNIT_FPGA U(3) 46 #define TEGRA_PRE_SI_ASIM_QT U(4) 47 #define TEGRA_PRE_SI_ASIM_LINSIM U(5) 48 #define TEGRA_PRE_SI_DSIM_ASIM_LINSIM U(6) 49 #define TEGRA_PRE_SI_VDK U(8) 50 51 /* 52 * Read the chip ID value 53 */ 54 static uint32_t tegra_get_chipid(void) 55 { 56 return mmio_read_32(TEGRA_MISC_BASE + HARDWARE_REVISION_OFFSET); 57 } 58 59 /* 60 * Read the chip's major version from chip ID value 61 */ 62 uint32_t tegra_get_chipid_major(void) 63 { 64 return (tegra_get_chipid() >> MAJOR_VERSION_SHIFT) & MAJOR_VERSION_MASK; 65 } 66 67 /* 68 * Read the chip's minor version from the chip ID value 69 */ 70 uint32_t tegra_get_chipid_minor(void) 71 { 72 return (tegra_get_chipid() >> MINOR_VERSION_SHIFT) & MINOR_VERSION_MASK; 73 } 74 75 /* 76 * Read the chip's pre_si_platform valus from the chip ID value 77 */ 78 static uint32_t tegra_get_chipid_pre_si_platform(void) 79 { 80 return (tegra_get_chipid() >> PRE_SI_PLATFORM_SHIFT) & PRE_SI_PLATFORM_MASK; 81 } 82 83 bool tegra_chipid_is_t132(void) 84 { 85 uint32_t chip_id = ((tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK); 86 87 return (chip_id == TEGRA_CHIPID_TEGRA13); 88 } 89 90 bool tegra_chipid_is_t186(void) 91 { 92 uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK; 93 94 return (chip_id == TEGRA_CHIPID_TEGRA18); 95 } 96 97 bool tegra_chipid_is_t210(void) 98 { 99 uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK; 100 101 return (chip_id == TEGRA_CHIPID_TEGRA21); 102 } 103 104 bool tegra_chipid_is_t210_b01(void) 105 { 106 return (tegra_chipid_is_t210() && (tegra_get_chipid_major() == 0x2U)); 107 } 108 109 /* 110 * Read the chip ID value and derive the platform 111 */ 112 static tegra_platform_t tegra_get_platform(void) 113 { 114 uint32_t major, minor, pre_si_platform; 115 tegra_platform_t ret; 116 117 /* get the major/minor chip ID values */ 118 major = tegra_get_chipid_major(); 119 minor = tegra_get_chipid_minor(); 120 pre_si_platform = tegra_get_chipid_pre_si_platform(); 121 122 if (major == 0U) { 123 /* 124 * The minor version number is used by simulation platforms 125 */ 126 switch (minor) { 127 /* 128 * Cadence's QuickTurn emulation system is a Solaris-based 129 * chip emulation system 130 */ 131 case TEGRA_MINOR_QT: 132 case TEGRA_MINOR_ASIM_QT: 133 ret = TEGRA_PLATFORM_QT; 134 break; 135 136 /* 137 * FPGAs are used during early software/hardware development 138 */ 139 case TEGRA_MINOR_FPGA: 140 ret = TEGRA_PLATFORM_FPGA; 141 break; 142 /* 143 * Linsim is a reconfigurable, clock-driven, mixed RTL/cmodel 144 * simulation framework. 145 */ 146 case TEGRA_MINOR_ASIM_LINSIM: 147 case TEGRA_MINOR_DSIM_ASIM_LINSIM: 148 ret = TEGRA_PLATFORM_LINSIM; 149 break; 150 151 /* 152 * Unit FPGAs run the actual hardware block IP on the FPGA with 153 * the other parts of the system using Linsim. 154 */ 155 case TEGRA_MINOR_UNIT_FPGA: 156 ret = TEGRA_PLATFORM_UNIT_FPGA; 157 break; 158 /* 159 * The Virtualizer Development Kit (VDK) is the standard chip 160 * development from Synopsis. 161 */ 162 case TEGRA_MINOR_VIRT_DEV_KIT: 163 ret = TEGRA_PLATFORM_VIRT_DEV_KIT; 164 break; 165 166 default: 167 ret = TEGRA_PLATFORM_MAX; 168 break; 169 } 170 171 } else if (pre_si_platform > 0U) { 172 173 switch (pre_si_platform) { 174 /* 175 * Cadence's QuickTurn emulation system is a Solaris-based 176 * chip emulation system 177 */ 178 case TEGRA_PRE_SI_QT: 179 case TEGRA_PRE_SI_ASIM_QT: 180 ret = TEGRA_PLATFORM_QT; 181 break; 182 183 /* 184 * FPGAs are used during early software/hardware development 185 */ 186 case TEGRA_PRE_SI_FPGA: 187 ret = TEGRA_PLATFORM_FPGA; 188 break; 189 /* 190 * Linsim is a reconfigurable, clock-driven, mixed RTL/cmodel 191 * simulation framework. 192 */ 193 case TEGRA_PRE_SI_ASIM_LINSIM: 194 case TEGRA_PRE_SI_DSIM_ASIM_LINSIM: 195 ret = TEGRA_PLATFORM_LINSIM; 196 break; 197 198 /* 199 * Unit FPGAs run the actual hardware block IP on the FPGA with 200 * the other parts of the system using Linsim. 201 */ 202 case TEGRA_PRE_SI_UNIT_FPGA: 203 ret = TEGRA_PLATFORM_UNIT_FPGA; 204 break; 205 /* 206 * The Virtualizer Development Kit (VDK) is the standard chip 207 * development from Synopsis. 208 */ 209 case TEGRA_PRE_SI_VDK: 210 ret = TEGRA_PLATFORM_VIRT_DEV_KIT; 211 break; 212 213 default: 214 ret = TEGRA_PLATFORM_MAX; 215 break; 216 } 217 218 } else { 219 /* Actual silicon platforms have a non-zero major version */ 220 ret = TEGRA_PLATFORM_SILICON; 221 } 222 223 return ret; 224 } 225 226 bool tegra_platform_is_silicon(void) 227 { 228 return ((tegra_get_platform() == TEGRA_PLATFORM_SILICON) ? true : false); 229 } 230 231 bool tegra_platform_is_qt(void) 232 { 233 return ((tegra_get_platform() == TEGRA_PLATFORM_QT) ? true : false); 234 } 235 236 bool tegra_platform_is_linsim(void) 237 { 238 tegra_platform_t plat = tegra_get_platform(); 239 240 return (((plat == TEGRA_PLATFORM_LINSIM) || 241 (plat == TEGRA_PLATFORM_UNIT_FPGA)) ? true : false); 242 } 243 244 bool tegra_platform_is_fpga(void) 245 { 246 return ((tegra_get_platform() == TEGRA_PLATFORM_FPGA) ? true : false); 247 } 248 249 bool tegra_platform_is_emulation(void) 250 { 251 return (tegra_get_platform() == TEGRA_PLATFORM_EMULATION); 252 } 253 254 bool tegra_platform_is_unit_fpga(void) 255 { 256 return ((tegra_get_platform() == TEGRA_PLATFORM_UNIT_FPGA) ? true : false); 257 } 258 259 bool tegra_platform_is_virt_dev_kit(void) 260 { 261 return ((tegra_get_platform() == TEGRA_PLATFORM_VIRT_DEV_KIT) ? true : false); 262 } 263 264 /* 265 * This function returns soc version which mainly consist of below fields 266 * 267 * soc_version[30:24] = JEP-106 continuation code for the SiP 268 * soc_version[23:16] = JEP-106 identification code with parity bit for the SiP 269 * soc_version[0:15] = chip identification 270 */ 271 int32_t plat_get_soc_version(void) 272 { 273 uint32_t chip_id = ((tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK); 274 uint32_t manfid = (JEDEC_NVIDIA_BKID << 24) | (JEDEC_NVIDIA_MFID << 16); 275 276 return (int32_t)(manfid | (chip_id & 0xFFFF)); 277 } 278 279 /* 280 * This function returns soc revision in below format 281 * 282 * soc_revision[8:15] = major version number 283 * soc_revision[0:7] = minor version number 284 */ 285 int32_t plat_get_soc_revision(void) 286 { 287 return (int32_t)((tegra_get_chipid_major() << 8) | tegra_get_chipid_minor()); 288 } 289