1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <mmio.h> 33 #include <tegra_def.h> 34 #include <tegra_platform.h> 35 #include <tegra_private.h> 36 37 /******************************************************************************* 38 * Tegra platforms 39 ******************************************************************************/ 40 typedef enum tegra_platform { 41 TEGRA_PLATFORM_SILICON = 0, 42 TEGRA_PLATFORM_QT, 43 TEGRA_PLATFORM_FPGA, 44 TEGRA_PLATFORM_EMULATION, 45 TEGRA_PLATFORM_MAX, 46 } tegra_platform_t; 47 48 /******************************************************************************* 49 * Tegra macros defining all the SoC minor versions 50 ******************************************************************************/ 51 #define TEGRA_MINOR_QT 0 52 #define TEGRA_MINOR_FPGA 1 53 #define TEGRA_MINOR_EMULATION_MIN 2 54 #define TEGRA_MINOR_EMULATION_MAX 10 55 56 /******************************************************************************* 57 * Tegra major, minor version helper macros 58 ******************************************************************************/ 59 #define MAJOR_VERSION_SHIFT 0x4 60 #define MAJOR_VERSION_MASK 0xF 61 #define MINOR_VERSION_SHIFT 0x10 62 #define MINOR_VERSION_MASK 0xF 63 #define CHIP_ID_SHIFT 8 64 #define CHIP_ID_MASK 0xFF 65 66 /******************************************************************************* 67 * Tegra chip ID values 68 ******************************************************************************/ 69 typedef enum tegra_chipid { 70 TEGRA_CHIPID_TEGRA13 = 0x13, 71 TEGRA_CHIPID_TEGRA21 = 0x21, 72 } tegra_chipid_t; 73 74 /* 75 * Read the chip ID value 76 */ 77 static uint32_t tegra_get_chipid(void) 78 { 79 return mmio_read_32(TEGRA_MISC_BASE + HARDWARE_REVISION_OFFSET); 80 } 81 82 /* 83 * Read the chip's major version from chip ID value 84 */ 85 uint32_t tegra_get_chipid_major(void) 86 { 87 return (tegra_get_chipid() >> MAJOR_VERSION_SHIFT) & MAJOR_VERSION_MASK; 88 } 89 90 /* 91 * Read the chip's minor version from the chip ID value 92 */ 93 uint32_t tegra_get_chipid_minor(void) 94 { 95 return (tegra_get_chipid() >> MINOR_VERSION_SHIFT) & MINOR_VERSION_MASK; 96 } 97 98 uint8_t tegra_chipid_is_t132(void) 99 { 100 uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK; 101 102 return (chip_id == TEGRA_CHIPID_TEGRA13); 103 } 104 105 uint8_t tegra_chipid_is_t210(void) 106 { 107 uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK; 108 109 return (chip_id == TEGRA_CHIPID_TEGRA21); 110 } 111 112 /* 113 * Read the chip ID value and derive the platform 114 */ 115 static tegra_platform_t tegra_get_platform(void) 116 { 117 uint32_t major = tegra_get_chipid_major(); 118 uint32_t minor = tegra_get_chipid_minor(); 119 120 /* Actual silicon platforms have a non-zero major version */ 121 if (major > 0) 122 return TEGRA_PLATFORM_SILICON; 123 124 /* 125 * The minor version number is used by simulation platforms 126 */ 127 128 /* 129 * Cadence's QuickTurn emulation system is a Solaris-based 130 * chip emulation system 131 */ 132 if (minor == TEGRA_MINOR_QT) 133 return TEGRA_PLATFORM_QT; 134 135 /* 136 * FPGAs are used during early software/hardware development 137 */ 138 if (minor == TEGRA_MINOR_FPGA) 139 return TEGRA_PLATFORM_FPGA; 140 141 /* Minor version reserved for other emulation platforms */ 142 if ((minor > TEGRA_MINOR_FPGA) && (minor <= TEGRA_MINOR_EMULATION_MAX)) 143 return TEGRA_PLATFORM_EMULATION; 144 145 /* unsupported platform */ 146 return TEGRA_PLATFORM_MAX; 147 } 148 149 uint8_t tegra_platform_is_silicon(void) 150 { 151 return (tegra_get_platform() == TEGRA_PLATFORM_SILICON); 152 } 153 154 uint8_t tegra_platform_is_qt(void) 155 { 156 return (tegra_get_platform() == TEGRA_PLATFORM_QT); 157 } 158 159 uint8_t tegra_platform_is_fpga(void) 160 { 161 return (tegra_get_platform() == TEGRA_PLATFORM_FPGA); 162 } 163 164 uint8_t tegra_platform_is_emulation(void) 165 { 166 return (tegra_get_platform() == TEGRA_PLATFORM_EMULATION); 167 } 168