1e954ab8fSVarun Wadekar /* 2e954ab8fSVarun Wadekar * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3e954ab8fSVarun Wadekar * 4e954ab8fSVarun Wadekar * Redistribution and use in source and binary forms, with or without 5e954ab8fSVarun Wadekar * modification, are permitted provided that the following conditions are met: 6e954ab8fSVarun Wadekar * 7e954ab8fSVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 8e954ab8fSVarun Wadekar * list of conditions and the following disclaimer. 9e954ab8fSVarun Wadekar * 10e954ab8fSVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 11e954ab8fSVarun Wadekar * this list of conditions and the following disclaimer in the documentation 12e954ab8fSVarun Wadekar * and/or other materials provided with the distribution. 13e954ab8fSVarun Wadekar * 14e954ab8fSVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 15e954ab8fSVarun Wadekar * to endorse or promote products derived from this software without specific 16e954ab8fSVarun Wadekar * prior written permission. 17e954ab8fSVarun Wadekar * 18e954ab8fSVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19e954ab8fSVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20e954ab8fSVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21e954ab8fSVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22e954ab8fSVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23e954ab8fSVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24e954ab8fSVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25e954ab8fSVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26e954ab8fSVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27e954ab8fSVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28e954ab8fSVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 29e954ab8fSVarun Wadekar */ 30e954ab8fSVarun Wadekar 31e954ab8fSVarun Wadekar #include <arch_helpers.h> 32e954ab8fSVarun Wadekar #include <mmio.h> 33e954ab8fSVarun Wadekar #include <tegra_def.h> 34e954ab8fSVarun Wadekar #include <tegra_platform.h> 35e954ab8fSVarun Wadekar #include <tegra_private.h> 36e954ab8fSVarun Wadekar 37e954ab8fSVarun Wadekar /******************************************************************************* 38e954ab8fSVarun Wadekar * Tegra platforms 39e954ab8fSVarun Wadekar ******************************************************************************/ 40e954ab8fSVarun Wadekar typedef enum tegra_platform { 41e954ab8fSVarun Wadekar TEGRA_PLATFORM_SILICON = 0, 42e954ab8fSVarun Wadekar TEGRA_PLATFORM_QT, 43e954ab8fSVarun Wadekar TEGRA_PLATFORM_FPGA, 44e954ab8fSVarun Wadekar TEGRA_PLATFORM_EMULATION, 45e954ab8fSVarun Wadekar TEGRA_PLATFORM_MAX, 46e954ab8fSVarun Wadekar } tegra_platform_t; 47e954ab8fSVarun Wadekar 48e954ab8fSVarun Wadekar /******************************************************************************* 49e954ab8fSVarun Wadekar * Tegra macros defining all the SoC minor versions 50e954ab8fSVarun Wadekar ******************************************************************************/ 51e954ab8fSVarun Wadekar #define TEGRA_MINOR_QT 0 52e954ab8fSVarun Wadekar #define TEGRA_MINOR_FPGA 1 53e954ab8fSVarun Wadekar #define TEGRA_MINOR_EMULATION_MIN 2 54e954ab8fSVarun Wadekar #define TEGRA_MINOR_EMULATION_MAX 10 55e954ab8fSVarun Wadekar 56e954ab8fSVarun Wadekar /******************************************************************************* 57e954ab8fSVarun Wadekar * Tegra major, minor version helper macros 58e954ab8fSVarun Wadekar ******************************************************************************/ 59e954ab8fSVarun Wadekar #define MAJOR_VERSION_SHIFT 0x4 60e954ab8fSVarun Wadekar #define MAJOR_VERSION_MASK 0xF 61e954ab8fSVarun Wadekar #define MINOR_VERSION_SHIFT 0x10 62e954ab8fSVarun Wadekar #define MINOR_VERSION_MASK 0xF 63e954ab8fSVarun Wadekar #define CHIP_ID_SHIFT 8 64e954ab8fSVarun Wadekar #define CHIP_ID_MASK 0xFF 65e954ab8fSVarun Wadekar 66e954ab8fSVarun Wadekar /******************************************************************************* 67e954ab8fSVarun Wadekar * Tegra chip ID values 68e954ab8fSVarun Wadekar ******************************************************************************/ 69e954ab8fSVarun Wadekar typedef enum tegra_chipid { 70e954ab8fSVarun Wadekar TEGRA_CHIPID_TEGRA13 = 0x13, 71e954ab8fSVarun Wadekar TEGRA_CHIPID_TEGRA21 = 0x21, 72*cd3de432SVarun Wadekar TEGRA_CHIPID_TEGRA18 = 0x18, 73e954ab8fSVarun Wadekar } tegra_chipid_t; 74e954ab8fSVarun Wadekar 75e954ab8fSVarun Wadekar /* 76e954ab8fSVarun Wadekar * Read the chip ID value 77e954ab8fSVarun Wadekar */ 78e954ab8fSVarun Wadekar static uint32_t tegra_get_chipid(void) 79e954ab8fSVarun Wadekar { 80e954ab8fSVarun Wadekar return mmio_read_32(TEGRA_MISC_BASE + HARDWARE_REVISION_OFFSET); 81e954ab8fSVarun Wadekar } 82e954ab8fSVarun Wadekar 83e954ab8fSVarun Wadekar /* 84e954ab8fSVarun Wadekar * Read the chip's major version from chip ID value 85e954ab8fSVarun Wadekar */ 86ea6dec5dSVarun Wadekar uint32_t tegra_get_chipid_major(void) 87e954ab8fSVarun Wadekar { 88e954ab8fSVarun Wadekar return (tegra_get_chipid() >> MAJOR_VERSION_SHIFT) & MAJOR_VERSION_MASK; 89e954ab8fSVarun Wadekar } 90e954ab8fSVarun Wadekar 91e954ab8fSVarun Wadekar /* 92e954ab8fSVarun Wadekar * Read the chip's minor version from the chip ID value 93e954ab8fSVarun Wadekar */ 94ea6dec5dSVarun Wadekar uint32_t tegra_get_chipid_minor(void) 95e954ab8fSVarun Wadekar { 96e954ab8fSVarun Wadekar return (tegra_get_chipid() >> MINOR_VERSION_SHIFT) & MINOR_VERSION_MASK; 97e954ab8fSVarun Wadekar } 98e954ab8fSVarun Wadekar 99e954ab8fSVarun Wadekar uint8_t tegra_chipid_is_t132(void) 100e954ab8fSVarun Wadekar { 101e954ab8fSVarun Wadekar uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK; 102e954ab8fSVarun Wadekar 103e954ab8fSVarun Wadekar return (chip_id == TEGRA_CHIPID_TEGRA13); 104e954ab8fSVarun Wadekar } 105e954ab8fSVarun Wadekar 106e954ab8fSVarun Wadekar uint8_t tegra_chipid_is_t210(void) 107e954ab8fSVarun Wadekar { 108e954ab8fSVarun Wadekar uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK; 109e954ab8fSVarun Wadekar 110e954ab8fSVarun Wadekar return (chip_id == TEGRA_CHIPID_TEGRA21); 111e954ab8fSVarun Wadekar } 112e954ab8fSVarun Wadekar 113*cd3de432SVarun Wadekar uint8_t tegra_chipid_is_t186(void) 114*cd3de432SVarun Wadekar { 115*cd3de432SVarun Wadekar uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK; 116*cd3de432SVarun Wadekar 117*cd3de432SVarun Wadekar return (chip_id == TEGRA_CHIPID_TEGRA18); 118*cd3de432SVarun Wadekar } 119*cd3de432SVarun Wadekar 120e954ab8fSVarun Wadekar /* 121e954ab8fSVarun Wadekar * Read the chip ID value and derive the platform 122e954ab8fSVarun Wadekar */ 123e954ab8fSVarun Wadekar static tegra_platform_t tegra_get_platform(void) 124e954ab8fSVarun Wadekar { 125e954ab8fSVarun Wadekar uint32_t major = tegra_get_chipid_major(); 126e954ab8fSVarun Wadekar uint32_t minor = tegra_get_chipid_minor(); 127e954ab8fSVarun Wadekar 128e954ab8fSVarun Wadekar /* Actual silicon platforms have a non-zero major version */ 129e954ab8fSVarun Wadekar if (major > 0) 130e954ab8fSVarun Wadekar return TEGRA_PLATFORM_SILICON; 131e954ab8fSVarun Wadekar 132e954ab8fSVarun Wadekar /* 133e954ab8fSVarun Wadekar * The minor version number is used by simulation platforms 134e954ab8fSVarun Wadekar */ 135e954ab8fSVarun Wadekar 136e954ab8fSVarun Wadekar /* 137e954ab8fSVarun Wadekar * Cadence's QuickTurn emulation system is a Solaris-based 138e954ab8fSVarun Wadekar * chip emulation system 139e954ab8fSVarun Wadekar */ 140e954ab8fSVarun Wadekar if (minor == TEGRA_MINOR_QT) 141e954ab8fSVarun Wadekar return TEGRA_PLATFORM_QT; 142e954ab8fSVarun Wadekar 143e954ab8fSVarun Wadekar /* 144e954ab8fSVarun Wadekar * FPGAs are used during early software/hardware development 145e954ab8fSVarun Wadekar */ 146e954ab8fSVarun Wadekar if (minor == TEGRA_MINOR_FPGA) 147e954ab8fSVarun Wadekar return TEGRA_PLATFORM_FPGA; 148e954ab8fSVarun Wadekar 149e954ab8fSVarun Wadekar /* Minor version reserved for other emulation platforms */ 150e954ab8fSVarun Wadekar if ((minor > TEGRA_MINOR_FPGA) && (minor <= TEGRA_MINOR_EMULATION_MAX)) 151e954ab8fSVarun Wadekar return TEGRA_PLATFORM_EMULATION; 152e954ab8fSVarun Wadekar 153e954ab8fSVarun Wadekar /* unsupported platform */ 154e954ab8fSVarun Wadekar return TEGRA_PLATFORM_MAX; 155e954ab8fSVarun Wadekar } 156e954ab8fSVarun Wadekar 157e954ab8fSVarun Wadekar uint8_t tegra_platform_is_silicon(void) 158e954ab8fSVarun Wadekar { 159e954ab8fSVarun Wadekar return (tegra_get_platform() == TEGRA_PLATFORM_SILICON); 160e954ab8fSVarun Wadekar } 161e954ab8fSVarun Wadekar 162e954ab8fSVarun Wadekar uint8_t tegra_platform_is_qt(void) 163e954ab8fSVarun Wadekar { 164e954ab8fSVarun Wadekar return (tegra_get_platform() == TEGRA_PLATFORM_QT); 165e954ab8fSVarun Wadekar } 166e954ab8fSVarun Wadekar 167e954ab8fSVarun Wadekar uint8_t tegra_platform_is_fpga(void) 168e954ab8fSVarun Wadekar { 169e954ab8fSVarun Wadekar return (tegra_get_platform() == TEGRA_PLATFORM_FPGA); 170e954ab8fSVarun Wadekar } 171e954ab8fSVarun Wadekar 172e954ab8fSVarun Wadekar uint8_t tegra_platform_is_emulation(void) 173e954ab8fSVarun Wadekar { 174e954ab8fSVarun Wadekar return (tegra_get_platform() == TEGRA_PLATFORM_EMULATION); 175e954ab8fSVarun Wadekar } 176