1e954ab8fSVarun Wadekar /* 2e954ab8fSVarun Wadekar * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3e954ab8fSVarun Wadekar * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5e954ab8fSVarun Wadekar */ 6e954ab8fSVarun Wadekar 7e954ab8fSVarun Wadekar #include <arch_helpers.h> 8e954ab8fSVarun Wadekar #include <mmio.h> 9e954ab8fSVarun Wadekar #include <tegra_def.h> 10e954ab8fSVarun Wadekar #include <tegra_platform.h> 11e954ab8fSVarun Wadekar #include <tegra_private.h> 12e954ab8fSVarun Wadekar 13e954ab8fSVarun Wadekar /******************************************************************************* 14e954ab8fSVarun Wadekar * Tegra platforms 15e954ab8fSVarun Wadekar ******************************************************************************/ 16e954ab8fSVarun Wadekar typedef enum tegra_platform { 17e954ab8fSVarun Wadekar TEGRA_PLATFORM_SILICON = 0, 18e954ab8fSVarun Wadekar TEGRA_PLATFORM_QT, 19e954ab8fSVarun Wadekar TEGRA_PLATFORM_FPGA, 20e954ab8fSVarun Wadekar TEGRA_PLATFORM_EMULATION, 21e954ab8fSVarun Wadekar TEGRA_PLATFORM_MAX, 22e954ab8fSVarun Wadekar } tegra_platform_t; 23e954ab8fSVarun Wadekar 24e954ab8fSVarun Wadekar /******************************************************************************* 25e954ab8fSVarun Wadekar * Tegra macros defining all the SoC minor versions 26e954ab8fSVarun Wadekar ******************************************************************************/ 27e954ab8fSVarun Wadekar #define TEGRA_MINOR_QT 0 28e954ab8fSVarun Wadekar #define TEGRA_MINOR_FPGA 1 29e954ab8fSVarun Wadekar #define TEGRA_MINOR_EMULATION_MIN 2 30e954ab8fSVarun Wadekar #define TEGRA_MINOR_EMULATION_MAX 10 31e954ab8fSVarun Wadekar 32e954ab8fSVarun Wadekar /******************************************************************************* 33e954ab8fSVarun Wadekar * Tegra major, minor version helper macros 34e954ab8fSVarun Wadekar ******************************************************************************/ 35e954ab8fSVarun Wadekar #define MAJOR_VERSION_SHIFT 0x4 36e954ab8fSVarun Wadekar #define MAJOR_VERSION_MASK 0xF 37e954ab8fSVarun Wadekar #define MINOR_VERSION_SHIFT 0x10 38e954ab8fSVarun Wadekar #define MINOR_VERSION_MASK 0xF 39e954ab8fSVarun Wadekar #define CHIP_ID_SHIFT 8 40e954ab8fSVarun Wadekar #define CHIP_ID_MASK 0xFF 41e954ab8fSVarun Wadekar 42e954ab8fSVarun Wadekar /******************************************************************************* 43e954ab8fSVarun Wadekar * Tegra chip ID values 44e954ab8fSVarun Wadekar ******************************************************************************/ 45e954ab8fSVarun Wadekar typedef enum tegra_chipid { 46e954ab8fSVarun Wadekar TEGRA_CHIPID_TEGRA13 = 0x13, 47e954ab8fSVarun Wadekar TEGRA_CHIPID_TEGRA21 = 0x21, 48cd3de432SVarun Wadekar TEGRA_CHIPID_TEGRA18 = 0x18, 49e954ab8fSVarun Wadekar } tegra_chipid_t; 50e954ab8fSVarun Wadekar 51e954ab8fSVarun Wadekar /* 52e954ab8fSVarun Wadekar * Read the chip ID value 53e954ab8fSVarun Wadekar */ 54e954ab8fSVarun Wadekar static uint32_t tegra_get_chipid(void) 55e954ab8fSVarun Wadekar { 56e954ab8fSVarun Wadekar return mmio_read_32(TEGRA_MISC_BASE + HARDWARE_REVISION_OFFSET); 57e954ab8fSVarun Wadekar } 58e954ab8fSVarun Wadekar 59e954ab8fSVarun Wadekar /* 60e954ab8fSVarun Wadekar * Read the chip's major version from chip ID value 61e954ab8fSVarun Wadekar */ 62ea6dec5dSVarun Wadekar uint32_t tegra_get_chipid_major(void) 63e954ab8fSVarun Wadekar { 64e954ab8fSVarun Wadekar return (tegra_get_chipid() >> MAJOR_VERSION_SHIFT) & MAJOR_VERSION_MASK; 65e954ab8fSVarun Wadekar } 66e954ab8fSVarun Wadekar 67e954ab8fSVarun Wadekar /* 68e954ab8fSVarun Wadekar * Read the chip's minor version from the chip ID value 69e954ab8fSVarun Wadekar */ 70ea6dec5dSVarun Wadekar uint32_t tegra_get_chipid_minor(void) 71e954ab8fSVarun Wadekar { 72e954ab8fSVarun Wadekar return (tegra_get_chipid() >> MINOR_VERSION_SHIFT) & MINOR_VERSION_MASK; 73e954ab8fSVarun Wadekar } 74e954ab8fSVarun Wadekar 75e954ab8fSVarun Wadekar uint8_t tegra_chipid_is_t132(void) 76e954ab8fSVarun Wadekar { 77e954ab8fSVarun Wadekar uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK; 78e954ab8fSVarun Wadekar 79e954ab8fSVarun Wadekar return (chip_id == TEGRA_CHIPID_TEGRA13); 80e954ab8fSVarun Wadekar } 81e954ab8fSVarun Wadekar 82e954ab8fSVarun Wadekar uint8_t tegra_chipid_is_t210(void) 83e954ab8fSVarun Wadekar { 84e954ab8fSVarun Wadekar uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK; 85e954ab8fSVarun Wadekar 86e954ab8fSVarun Wadekar return (chip_id == TEGRA_CHIPID_TEGRA21); 87e954ab8fSVarun Wadekar } 88e954ab8fSVarun Wadekar 89cd3de432SVarun Wadekar uint8_t tegra_chipid_is_t186(void) 90cd3de432SVarun Wadekar { 91cd3de432SVarun Wadekar uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK; 92cd3de432SVarun Wadekar 93cd3de432SVarun Wadekar return (chip_id == TEGRA_CHIPID_TEGRA18); 94cd3de432SVarun Wadekar } 95cd3de432SVarun Wadekar 96e954ab8fSVarun Wadekar /* 97e954ab8fSVarun Wadekar * Read the chip ID value and derive the platform 98e954ab8fSVarun Wadekar */ 99e954ab8fSVarun Wadekar static tegra_platform_t tegra_get_platform(void) 100e954ab8fSVarun Wadekar { 101e954ab8fSVarun Wadekar uint32_t major = tegra_get_chipid_major(); 102e954ab8fSVarun Wadekar uint32_t minor = tegra_get_chipid_minor(); 103e954ab8fSVarun Wadekar 104e954ab8fSVarun Wadekar /* Actual silicon platforms have a non-zero major version */ 105e954ab8fSVarun Wadekar if (major > 0) 106e954ab8fSVarun Wadekar return TEGRA_PLATFORM_SILICON; 107e954ab8fSVarun Wadekar 108e954ab8fSVarun Wadekar /* 109e954ab8fSVarun Wadekar * The minor version number is used by simulation platforms 110e954ab8fSVarun Wadekar */ 111e954ab8fSVarun Wadekar 112e954ab8fSVarun Wadekar /* 113e954ab8fSVarun Wadekar * Cadence's QuickTurn emulation system is a Solaris-based 114e954ab8fSVarun Wadekar * chip emulation system 115e954ab8fSVarun Wadekar */ 116e954ab8fSVarun Wadekar if (minor == TEGRA_MINOR_QT) 117e954ab8fSVarun Wadekar return TEGRA_PLATFORM_QT; 118e954ab8fSVarun Wadekar 119e954ab8fSVarun Wadekar /* 120e954ab8fSVarun Wadekar * FPGAs are used during early software/hardware development 121e954ab8fSVarun Wadekar */ 122e954ab8fSVarun Wadekar if (minor == TEGRA_MINOR_FPGA) 123e954ab8fSVarun Wadekar return TEGRA_PLATFORM_FPGA; 124e954ab8fSVarun Wadekar 125e954ab8fSVarun Wadekar /* Minor version reserved for other emulation platforms */ 126e954ab8fSVarun Wadekar if ((minor > TEGRA_MINOR_FPGA) && (minor <= TEGRA_MINOR_EMULATION_MAX)) 127e954ab8fSVarun Wadekar return TEGRA_PLATFORM_EMULATION; 128e954ab8fSVarun Wadekar 129e954ab8fSVarun Wadekar /* unsupported platform */ 130e954ab8fSVarun Wadekar return TEGRA_PLATFORM_MAX; 131e954ab8fSVarun Wadekar } 132e954ab8fSVarun Wadekar 133e954ab8fSVarun Wadekar uint8_t tegra_platform_is_silicon(void) 134e954ab8fSVarun Wadekar { 135e954ab8fSVarun Wadekar return (tegra_get_platform() == TEGRA_PLATFORM_SILICON); 136e954ab8fSVarun Wadekar } 137e954ab8fSVarun Wadekar 138e954ab8fSVarun Wadekar uint8_t tegra_platform_is_qt(void) 139e954ab8fSVarun Wadekar { 140e954ab8fSVarun Wadekar return (tegra_get_platform() == TEGRA_PLATFORM_QT); 141e954ab8fSVarun Wadekar } 142e954ab8fSVarun Wadekar 143e954ab8fSVarun Wadekar uint8_t tegra_platform_is_fpga(void) 144e954ab8fSVarun Wadekar { 145e954ab8fSVarun Wadekar return (tegra_get_platform() == TEGRA_PLATFORM_FPGA); 146e954ab8fSVarun Wadekar } 147e954ab8fSVarun Wadekar 148e954ab8fSVarun Wadekar uint8_t tegra_platform_is_emulation(void) 149e954ab8fSVarun Wadekar { 150e954ab8fSVarun Wadekar return (tegra_get_platform() == TEGRA_PLATFORM_EMULATION); 151e954ab8fSVarun Wadekar } 152