1e954ab8fSVarun Wadekar /* 2e954ab8fSVarun Wadekar * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3e954ab8fSVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5e954ab8fSVarun Wadekar */ 6e954ab8fSVarun Wadekar 7e954ab8fSVarun Wadekar #include <arch_helpers.h> 8*09d40e0eSAntonio Nino Diaz #include <lib/mmio.h> 9*09d40e0eSAntonio Nino Diaz 10e954ab8fSVarun Wadekar #include <tegra_def.h> 11e954ab8fSVarun Wadekar #include <tegra_platform.h> 12e954ab8fSVarun Wadekar #include <tegra_private.h> 13e954ab8fSVarun Wadekar 14e954ab8fSVarun Wadekar /******************************************************************************* 15e954ab8fSVarun Wadekar * Tegra platforms 16e954ab8fSVarun Wadekar ******************************************************************************/ 17e954ab8fSVarun Wadekar typedef enum tegra_platform { 18e954ab8fSVarun Wadekar TEGRA_PLATFORM_SILICON = 0, 19e954ab8fSVarun Wadekar TEGRA_PLATFORM_QT, 20e954ab8fSVarun Wadekar TEGRA_PLATFORM_FPGA, 21e954ab8fSVarun Wadekar TEGRA_PLATFORM_EMULATION, 22e954ab8fSVarun Wadekar TEGRA_PLATFORM_MAX, 23e954ab8fSVarun Wadekar } tegra_platform_t; 24e954ab8fSVarun Wadekar 25e954ab8fSVarun Wadekar /******************************************************************************* 26e954ab8fSVarun Wadekar * Tegra macros defining all the SoC minor versions 27e954ab8fSVarun Wadekar ******************************************************************************/ 28e954ab8fSVarun Wadekar #define TEGRA_MINOR_QT 0 29e954ab8fSVarun Wadekar #define TEGRA_MINOR_FPGA 1 30e954ab8fSVarun Wadekar #define TEGRA_MINOR_EMULATION_MIN 2 31e954ab8fSVarun Wadekar #define TEGRA_MINOR_EMULATION_MAX 10 32e954ab8fSVarun Wadekar 33e954ab8fSVarun Wadekar /******************************************************************************* 34e954ab8fSVarun Wadekar * Tegra major, minor version helper macros 35e954ab8fSVarun Wadekar ******************************************************************************/ 36e954ab8fSVarun Wadekar #define MAJOR_VERSION_SHIFT 0x4 37e954ab8fSVarun Wadekar #define MAJOR_VERSION_MASK 0xF 38e954ab8fSVarun Wadekar #define MINOR_VERSION_SHIFT 0x10 39e954ab8fSVarun Wadekar #define MINOR_VERSION_MASK 0xF 40e954ab8fSVarun Wadekar #define CHIP_ID_SHIFT 8 41e954ab8fSVarun Wadekar #define CHIP_ID_MASK 0xFF 42e954ab8fSVarun Wadekar 43e954ab8fSVarun Wadekar /******************************************************************************* 44e954ab8fSVarun Wadekar * Tegra chip ID values 45e954ab8fSVarun Wadekar ******************************************************************************/ 46e954ab8fSVarun Wadekar typedef enum tegra_chipid { 47e954ab8fSVarun Wadekar TEGRA_CHIPID_TEGRA13 = 0x13, 48e954ab8fSVarun Wadekar TEGRA_CHIPID_TEGRA21 = 0x21, 49cd3de432SVarun Wadekar TEGRA_CHIPID_TEGRA18 = 0x18, 50e954ab8fSVarun Wadekar } tegra_chipid_t; 51e954ab8fSVarun Wadekar 52e954ab8fSVarun Wadekar /* 53e954ab8fSVarun Wadekar * Read the chip ID value 54e954ab8fSVarun Wadekar */ 55e954ab8fSVarun Wadekar static uint32_t tegra_get_chipid(void) 56e954ab8fSVarun Wadekar { 57e954ab8fSVarun Wadekar return mmio_read_32(TEGRA_MISC_BASE + HARDWARE_REVISION_OFFSET); 58e954ab8fSVarun Wadekar } 59e954ab8fSVarun Wadekar 60e954ab8fSVarun Wadekar /* 61e954ab8fSVarun Wadekar * Read the chip's major version from chip ID value 62e954ab8fSVarun Wadekar */ 63ea6dec5dSVarun Wadekar uint32_t tegra_get_chipid_major(void) 64e954ab8fSVarun Wadekar { 65e954ab8fSVarun Wadekar return (tegra_get_chipid() >> MAJOR_VERSION_SHIFT) & MAJOR_VERSION_MASK; 66e954ab8fSVarun Wadekar } 67e954ab8fSVarun Wadekar 68e954ab8fSVarun Wadekar /* 69e954ab8fSVarun Wadekar * Read the chip's minor version from the chip ID value 70e954ab8fSVarun Wadekar */ 71ea6dec5dSVarun Wadekar uint32_t tegra_get_chipid_minor(void) 72e954ab8fSVarun Wadekar { 73e954ab8fSVarun Wadekar return (tegra_get_chipid() >> MINOR_VERSION_SHIFT) & MINOR_VERSION_MASK; 74e954ab8fSVarun Wadekar } 75e954ab8fSVarun Wadekar 76e954ab8fSVarun Wadekar uint8_t tegra_chipid_is_t132(void) 77e954ab8fSVarun Wadekar { 78e954ab8fSVarun Wadekar uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK; 79e954ab8fSVarun Wadekar 80e954ab8fSVarun Wadekar return (chip_id == TEGRA_CHIPID_TEGRA13); 81e954ab8fSVarun Wadekar } 82e954ab8fSVarun Wadekar 83e954ab8fSVarun Wadekar uint8_t tegra_chipid_is_t210(void) 84e954ab8fSVarun Wadekar { 85e954ab8fSVarun Wadekar uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK; 86e954ab8fSVarun Wadekar 87e954ab8fSVarun Wadekar return (chip_id == TEGRA_CHIPID_TEGRA21); 88e954ab8fSVarun Wadekar } 89e954ab8fSVarun Wadekar 90cd3de432SVarun Wadekar uint8_t tegra_chipid_is_t186(void) 91cd3de432SVarun Wadekar { 92cd3de432SVarun Wadekar uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK; 93cd3de432SVarun Wadekar 94cd3de432SVarun Wadekar return (chip_id == TEGRA_CHIPID_TEGRA18); 95cd3de432SVarun Wadekar } 96cd3de432SVarun Wadekar 97e954ab8fSVarun Wadekar /* 98e954ab8fSVarun Wadekar * Read the chip ID value and derive the platform 99e954ab8fSVarun Wadekar */ 100e954ab8fSVarun Wadekar static tegra_platform_t tegra_get_platform(void) 101e954ab8fSVarun Wadekar { 102e954ab8fSVarun Wadekar uint32_t major = tegra_get_chipid_major(); 103e954ab8fSVarun Wadekar uint32_t minor = tegra_get_chipid_minor(); 104e954ab8fSVarun Wadekar 105e954ab8fSVarun Wadekar /* Actual silicon platforms have a non-zero major version */ 106e954ab8fSVarun Wadekar if (major > 0) 107e954ab8fSVarun Wadekar return TEGRA_PLATFORM_SILICON; 108e954ab8fSVarun Wadekar 109e954ab8fSVarun Wadekar /* 110e954ab8fSVarun Wadekar * The minor version number is used by simulation platforms 111e954ab8fSVarun Wadekar */ 112e954ab8fSVarun Wadekar 113e954ab8fSVarun Wadekar /* 114e954ab8fSVarun Wadekar * Cadence's QuickTurn emulation system is a Solaris-based 115e954ab8fSVarun Wadekar * chip emulation system 116e954ab8fSVarun Wadekar */ 117e954ab8fSVarun Wadekar if (minor == TEGRA_MINOR_QT) 118e954ab8fSVarun Wadekar return TEGRA_PLATFORM_QT; 119e954ab8fSVarun Wadekar 120e954ab8fSVarun Wadekar /* 121e954ab8fSVarun Wadekar * FPGAs are used during early software/hardware development 122e954ab8fSVarun Wadekar */ 123e954ab8fSVarun Wadekar if (minor == TEGRA_MINOR_FPGA) 124e954ab8fSVarun Wadekar return TEGRA_PLATFORM_FPGA; 125e954ab8fSVarun Wadekar 126e954ab8fSVarun Wadekar /* Minor version reserved for other emulation platforms */ 127e954ab8fSVarun Wadekar if ((minor > TEGRA_MINOR_FPGA) && (minor <= TEGRA_MINOR_EMULATION_MAX)) 128e954ab8fSVarun Wadekar return TEGRA_PLATFORM_EMULATION; 129e954ab8fSVarun Wadekar 130e954ab8fSVarun Wadekar /* unsupported platform */ 131e954ab8fSVarun Wadekar return TEGRA_PLATFORM_MAX; 132e954ab8fSVarun Wadekar } 133e954ab8fSVarun Wadekar 134e954ab8fSVarun Wadekar uint8_t tegra_platform_is_silicon(void) 135e954ab8fSVarun Wadekar { 136e954ab8fSVarun Wadekar return (tegra_get_platform() == TEGRA_PLATFORM_SILICON); 137e954ab8fSVarun Wadekar } 138e954ab8fSVarun Wadekar 139e954ab8fSVarun Wadekar uint8_t tegra_platform_is_qt(void) 140e954ab8fSVarun Wadekar { 141e954ab8fSVarun Wadekar return (tegra_get_platform() == TEGRA_PLATFORM_QT); 142e954ab8fSVarun Wadekar } 143e954ab8fSVarun Wadekar 144e954ab8fSVarun Wadekar uint8_t tegra_platform_is_fpga(void) 145e954ab8fSVarun Wadekar { 146e954ab8fSVarun Wadekar return (tegra_get_platform() == TEGRA_PLATFORM_FPGA); 147e954ab8fSVarun Wadekar } 148e954ab8fSVarun Wadekar 149e954ab8fSVarun Wadekar uint8_t tegra_platform_is_emulation(void) 150e954ab8fSVarun Wadekar { 151e954ab8fSVarun Wadekar return (tegra_get_platform() == TEGRA_PLATFORM_EMULATION); 152e954ab8fSVarun Wadekar } 153