1*5e1b83aaSVarun Wadekar /* 2*5e1b83aaSVarun Wadekar * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 3*5e1b83aaSVarun Wadekar * 4*5e1b83aaSVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause 5*5e1b83aaSVarun Wadekar */ 6*5e1b83aaSVarun Wadekar 7*5e1b83aaSVarun Wadekar #include <assert.h> 8*5e1b83aaSVarun Wadekar 9*5e1b83aaSVarun Wadekar #include <common/bl_common.h> 10*5e1b83aaSVarun Wadekar #include <drivers/arm/gicv3.h> 11*5e1b83aaSVarun Wadekar #include <lib/utils.h> 12*5e1b83aaSVarun Wadekar 13*5e1b83aaSVarun Wadekar #include <plat/common/platform.h> 14*5e1b83aaSVarun Wadekar #include <platform_def.h> 15*5e1b83aaSVarun Wadekar #include <tegra_private.h> 16*5e1b83aaSVarun Wadekar #include <tegra_def.h> 17*5e1b83aaSVarun Wadekar 18*5e1b83aaSVarun Wadekar /* The GICv3 driver only needs to be initialized in EL3 */ 19*5e1b83aaSVarun Wadekar static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; 20*5e1b83aaSVarun Wadekar 21*5e1b83aaSVarun Wadekar static unsigned int plat_tegra_mpidr_to_core_pos(unsigned long mpidr) 22*5e1b83aaSVarun Wadekar { 23*5e1b83aaSVarun Wadekar return (unsigned int)plat_core_pos_by_mpidr(mpidr); 24*5e1b83aaSVarun Wadekar } 25*5e1b83aaSVarun Wadekar 26*5e1b83aaSVarun Wadekar /****************************************************************************** 27*5e1b83aaSVarun Wadekar * Tegra common helper to setup the GICv3 driver data. 28*5e1b83aaSVarun Wadekar *****************************************************************************/ 29*5e1b83aaSVarun Wadekar void tegra_gic_setup(const interrupt_prop_t *interrupt_props, 30*5e1b83aaSVarun Wadekar unsigned int interrupt_props_num) 31*5e1b83aaSVarun Wadekar { 32*5e1b83aaSVarun Wadekar /* 33*5e1b83aaSVarun Wadekar * Tegra GIC configuration settings 34*5e1b83aaSVarun Wadekar */ 35*5e1b83aaSVarun Wadekar static gicv3_driver_data_t tegra_gic_data; 36*5e1b83aaSVarun Wadekar 37*5e1b83aaSVarun Wadekar /* 38*5e1b83aaSVarun Wadekar * Register Tegra GICv3 driver 39*5e1b83aaSVarun Wadekar */ 40*5e1b83aaSVarun Wadekar tegra_gic_data.gicd_base = TEGRA_GICD_BASE; 41*5e1b83aaSVarun Wadekar tegra_gic_data.gicr_base = TEGRA_GICR_BASE; 42*5e1b83aaSVarun Wadekar tegra_gic_data.rdistif_num = PLATFORM_CORE_COUNT; 43*5e1b83aaSVarun Wadekar tegra_gic_data.rdistif_base_addrs = rdistif_base_addrs; 44*5e1b83aaSVarun Wadekar tegra_gic_data.mpidr_to_core_pos = plat_tegra_mpidr_to_core_pos; 45*5e1b83aaSVarun Wadekar tegra_gic_data.interrupt_props = interrupt_props; 46*5e1b83aaSVarun Wadekar tegra_gic_data.interrupt_props_num = interrupt_props_num; 47*5e1b83aaSVarun Wadekar gicv3_driver_init(&tegra_gic_data); 48*5e1b83aaSVarun Wadekar 49*5e1b83aaSVarun Wadekar /* initialize the GICD and GICR */ 50*5e1b83aaSVarun Wadekar tegra_gic_init(); 51*5e1b83aaSVarun Wadekar } 52*5e1b83aaSVarun Wadekar 53*5e1b83aaSVarun Wadekar /****************************************************************************** 54*5e1b83aaSVarun Wadekar * Tegra common helper to initialize the GICv3 only driver. 55*5e1b83aaSVarun Wadekar *****************************************************************************/ 56*5e1b83aaSVarun Wadekar void tegra_gic_init(void) 57*5e1b83aaSVarun Wadekar { 58*5e1b83aaSVarun Wadekar gicv3_distif_init(); 59*5e1b83aaSVarun Wadekar gicv3_rdistif_init(plat_my_core_pos()); 60*5e1b83aaSVarun Wadekar gicv3_cpuif_enable(plat_my_core_pos()); 61*5e1b83aaSVarun Wadekar } 62*5e1b83aaSVarun Wadekar 63*5e1b83aaSVarun Wadekar /****************************************************************************** 64*5e1b83aaSVarun Wadekar * Tegra common helper to disable the GICv3 CPU interface 65*5e1b83aaSVarun Wadekar *****************************************************************************/ 66*5e1b83aaSVarun Wadekar void tegra_gic_cpuif_deactivate(void) 67*5e1b83aaSVarun Wadekar { 68*5e1b83aaSVarun Wadekar gicv3_cpuif_disable(plat_my_core_pos()); 69*5e1b83aaSVarun Wadekar } 70*5e1b83aaSVarun Wadekar 71*5e1b83aaSVarun Wadekar /****************************************************************************** 72*5e1b83aaSVarun Wadekar * Tegra common helper to initialize the per cpu distributor interface 73*5e1b83aaSVarun Wadekar * in GICv3 74*5e1b83aaSVarun Wadekar *****************************************************************************/ 75*5e1b83aaSVarun Wadekar void tegra_gic_pcpu_init(void) 76*5e1b83aaSVarun Wadekar { 77*5e1b83aaSVarun Wadekar gicv3_rdistif_init(plat_my_core_pos()); 78*5e1b83aaSVarun Wadekar gicv3_cpuif_enable(plat_my_core_pos()); 79*5e1b83aaSVarun Wadekar } 80