1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch_helpers.h> 10 #include <bl31/interrupt_mgmt.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <context.h> 14 #include <denver.h> 15 #include <lib/bakery_lock.h> 16 #include <lib/el3_runtime/context_mgmt.h> 17 #include <plat/common/platform.h> 18 19 #include <tegra_def.h> 20 #include <tegra_private.h> 21 22 static DEFINE_BAKERY_LOCK(tegra_fiq_lock); 23 24 /******************************************************************************* 25 * Static variables 26 ******************************************************************************/ 27 static uint64_t ns_fiq_handler_addr; 28 static uint32_t fiq_handler_active; 29 static pcpu_fiq_state_t fiq_state[PLATFORM_CORE_COUNT]; 30 31 /******************************************************************************* 32 * Handler for FIQ interrupts 33 ******************************************************************************/ 34 static uint64_t tegra_fiq_interrupt_handler(uint32_t id, 35 uint32_t flags, 36 void *handle, 37 void *cookie) 38 { 39 cpu_context_t *ctx = cm_get_context(NON_SECURE); 40 el3_state_t *el3state_ctx = get_el3state_ctx(ctx); 41 uint32_t cpu = plat_my_core_pos(); 42 uint32_t irq; 43 44 (void)id; 45 (void)flags; 46 (void)handle; 47 (void)cookie; 48 49 bakery_lock_get(&tegra_fiq_lock); 50 51 /* 52 * The FIQ was generated when the execution was in the non-secure 53 * world. Save the context registers to start with. 54 */ 55 cm_el1_sysregs_context_save(NON_SECURE); 56 57 /* 58 * Save elr_el3 and spsr_el3 from the saved context, and overwrite 59 * the context with the NS fiq_handler_addr and SPSR value. 60 */ 61 fiq_state[cpu].elr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3)); 62 fiq_state[cpu].spsr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_SPSR_EL3)); 63 64 /* 65 * Set the new ELR to continue execution in the NS world using the 66 * FIQ handler registered earlier. 67 */ 68 assert(ns_fiq_handler_addr); 69 write_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3), (ns_fiq_handler_addr)); 70 71 /* 72 * Mark this interrupt as complete to avoid a FIQ storm. 73 */ 74 irq = plat_ic_acknowledge_interrupt(); 75 if (irq < 1022U) { 76 plat_ic_end_of_interrupt(irq); 77 } 78 79 bakery_lock_release(&tegra_fiq_lock); 80 81 return 0; 82 } 83 84 /******************************************************************************* 85 * Setup handler for FIQ interrupts 86 ******************************************************************************/ 87 void tegra_fiq_handler_setup(void) 88 { 89 uint32_t flags; 90 int32_t rc; 91 92 /* return if already registered */ 93 if (fiq_handler_active == 0U) { 94 /* 95 * Register an interrupt handler for FIQ interrupts generated for 96 * NS interrupt sources 97 */ 98 flags = 0U; 99 set_interrupt_rm_flag((flags), (NON_SECURE)); 100 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 101 tegra_fiq_interrupt_handler, 102 flags); 103 if (rc != 0) { 104 panic(); 105 } 106 107 /* handler is now active */ 108 fiq_handler_active = 1; 109 } 110 } 111 112 /******************************************************************************* 113 * Validate and store NS world's entrypoint for FIQ interrupts 114 ******************************************************************************/ 115 void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint) 116 { 117 ns_fiq_handler_addr = entrypoint; 118 } 119 120 /******************************************************************************* 121 * Handler to return the NS EL1/EL0 CPU context 122 ******************************************************************************/ 123 int32_t tegra_fiq_get_intr_context(void) 124 { 125 cpu_context_t *ctx = cm_get_context(NON_SECURE); 126 gp_regs_t *gpregs_ctx = get_gpregs_ctx(ctx); 127 const el1_sys_regs_t *el1state_ctx = get_sysregs_ctx(ctx); 128 uint32_t cpu = plat_my_core_pos(); 129 uint64_t val; 130 131 /* 132 * We store the ELR_EL3, SPSR_EL3, SP_EL0 and SP_EL1 registers so 133 * that el3_exit() sends these values back to the NS world. 134 */ 135 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X0), (fiq_state[cpu].elr_el3)); 136 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X1), (fiq_state[cpu].spsr_el3)); 137 138 val = read_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_SP_EL0)); 139 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X2), (val)); 140 141 val = read_ctx_reg((el1state_ctx), (uint32_t)(CTX_SP_EL1)); 142 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X3), (val)); 143 144 return 0; 145 } 146