1 /* 2 * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 10 #include <arch_helpers.h> 11 #include <bl31/interrupt_mgmt.h> 12 #include <bl31/ehf.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <denver.h> 17 #include <lib/el3_runtime/context_mgmt.h> 18 #include <plat/common/platform.h> 19 20 #if ENABLE_WDT_LEGACY_FIQ_HANDLING 21 #include <flowctrl.h> 22 #endif 23 #include <tegra_def.h> 24 #include <tegra_private.h> 25 26 /* Legacy FIQ used by earlier Tegra platforms */ 27 #define LEGACY_FIQ_PPI_WDT 28U 28 29 /* Install priority level descriptors for each dispatcher */ 30 ehf_pri_desc_t plat_exceptions[] = { 31 EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_TEGRA_WDT_PRIO), 32 }; 33 34 /* Expose priority descriptors to Exception Handling Framework */ 35 EHF_REGISTER_PRIORITIES(plat_exceptions, ARRAY_SIZE(plat_exceptions), 36 PLAT_PRI_BITS); 37 38 /******************************************************************************* 39 * Static variables 40 ******************************************************************************/ 41 static uint64_t ns_fiq_handler_addr; 42 static uint32_t fiq_handler_active; 43 static pcpu_fiq_state_t fiq_state[PLATFORM_CORE_COUNT]; 44 45 /******************************************************************************* 46 * Handler for FIQ interrupts 47 ******************************************************************************/ 48 static int tegra_fiq_interrupt_handler(unsigned int id, unsigned int flags, 49 void *handle, void *cookie) 50 { 51 cpu_context_t *ctx = cm_get_context(NON_SECURE); 52 el3_state_t *el3state_ctx = get_el3state_ctx(ctx); 53 uint32_t cpu = plat_my_core_pos(); 54 55 (void)flags; 56 (void)handle; 57 (void)cookie; 58 59 /* 60 * Jump to NS world only if the NS world's FIQ handler has 61 * been registered 62 */ 63 if (ns_fiq_handler_addr != 0U) { 64 65 /* 66 * The FIQ was generated when the execution was in the non-secure 67 * world. Save the context registers to start with. 68 */ 69 cm_el1_sysregs_context_save(NON_SECURE); 70 71 /* 72 * Save elr_el3 and spsr_el3 from the saved context, and overwrite 73 * the context with the NS fiq_handler_addr and SPSR value. 74 */ 75 fiq_state[cpu].elr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3)); 76 fiq_state[cpu].spsr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_SPSR_EL3)); 77 78 /* 79 * Set the new ELR to continue execution in the NS world using the 80 * FIQ handler registered earlier. 81 */ 82 cm_set_elr_el3(NON_SECURE, ns_fiq_handler_addr); 83 } 84 85 #if ENABLE_WDT_LEGACY_FIQ_HANDLING 86 /* 87 * Tegra platforms that use LEGACY_FIQ as the watchdog timer FIQ 88 * need to issue an IPI to other CPUs, to allow them to handle 89 * the "system hung" scenario. This interrupt is passed to the GICD 90 * via the Flow Controller. So, once we receive this interrupt, 91 * disable the routing so that we can mark it as "complete" in the 92 * GIC later. 93 */ 94 if (id == LEGACY_FIQ_PPI_WDT) { 95 tegra_fc_disable_fiq_to_ccplex_routing(); 96 } 97 #endif 98 99 /* 100 * Mark this interrupt as complete to avoid a FIQ storm. 101 */ 102 plat_ic_end_of_interrupt(id); 103 104 return 0; 105 } 106 107 /******************************************************************************* 108 * Setup handler for FIQ interrupts 109 ******************************************************************************/ 110 void tegra_fiq_handler_setup(void) 111 { 112 /* return if already registered */ 113 if (fiq_handler_active == 0U) { 114 /* 115 * Register an interrupt handler for FIQ interrupts generated for 116 * NS interrupt sources 117 */ 118 ehf_register_priority_handler(PLAT_TEGRA_WDT_PRIO, tegra_fiq_interrupt_handler); 119 120 /* handler is now active */ 121 fiq_handler_active = 1; 122 } 123 } 124 125 /******************************************************************************* 126 * Validate and store NS world's entrypoint for FIQ interrupts 127 ******************************************************************************/ 128 void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint) 129 { 130 ns_fiq_handler_addr = entrypoint; 131 } 132 133 /******************************************************************************* 134 * Handler to return the NS EL1/EL0 CPU context 135 ******************************************************************************/ 136 int32_t tegra_fiq_get_intr_context(void) 137 { 138 cpu_context_t *ctx = cm_get_context(NON_SECURE); 139 gp_regs_t *gpregs_ctx = get_gpregs_ctx(ctx); 140 const el1_sysregs_t *el1state_ctx = get_el1_sysregs_ctx(ctx); 141 uint32_t cpu = plat_my_core_pos(); 142 uint64_t val; 143 144 /* 145 * We store the ELR_EL3, SPSR_EL3, SP_EL0 and SP_EL1 registers so 146 * that el3_exit() sends these values back to the NS world. 147 */ 148 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X0), (fiq_state[cpu].elr_el3)); 149 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X1), (fiq_state[cpu].spsr_el3)); 150 151 val = read_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_SP_EL0)); 152 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X2), (val)); 153 154 val = read_ctx_reg((el1state_ctx), (uint32_t)(CTX_SP_EL1)); 155 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X3), (val)); 156 157 return 0; 158 } 159