1*78e2bd10SVarun Wadekar /* 2*78e2bd10SVarun Wadekar * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3*78e2bd10SVarun Wadekar * 4*78e2bd10SVarun Wadekar * Redistribution and use in source and binary forms, with or without 5*78e2bd10SVarun Wadekar * modification, are permitted provided that the following conditions are met: 6*78e2bd10SVarun Wadekar * 7*78e2bd10SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 8*78e2bd10SVarun Wadekar * list of conditions and the following disclaimer. 9*78e2bd10SVarun Wadekar * 10*78e2bd10SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 11*78e2bd10SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 12*78e2bd10SVarun Wadekar * and/or other materials provided with the distribution. 13*78e2bd10SVarun Wadekar * 14*78e2bd10SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 15*78e2bd10SVarun Wadekar * to endorse or promote products derived from this software without specific 16*78e2bd10SVarun Wadekar * prior written permission. 17*78e2bd10SVarun Wadekar * 18*78e2bd10SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*78e2bd10SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*78e2bd10SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*78e2bd10SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*78e2bd10SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*78e2bd10SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*78e2bd10SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*78e2bd10SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*78e2bd10SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*78e2bd10SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*78e2bd10SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 29*78e2bd10SVarun Wadekar */ 30*78e2bd10SVarun Wadekar 31*78e2bd10SVarun Wadekar #include <arch_helpers.h> 32*78e2bd10SVarun Wadekar #include <assert.h> 33*78e2bd10SVarun Wadekar #include <bakery_lock.h> 34*78e2bd10SVarun Wadekar #include <bl_common.h> 35*78e2bd10SVarun Wadekar #include <context.h> 36*78e2bd10SVarun Wadekar #include <context_mgmt.h> 37*78e2bd10SVarun Wadekar #include <debug.h> 38*78e2bd10SVarun Wadekar #include <denver.h> 39*78e2bd10SVarun Wadekar #include <gic_v2.h> 40*78e2bd10SVarun Wadekar #include <interrupt_mgmt.h> 41*78e2bd10SVarun Wadekar #include <platform.h> 42*78e2bd10SVarun Wadekar #include <tegra_def.h> 43*78e2bd10SVarun Wadekar #include <tegra_private.h> 44*78e2bd10SVarun Wadekar 45*78e2bd10SVarun Wadekar DEFINE_BAKERY_LOCK(tegra_fiq_lock); 46*78e2bd10SVarun Wadekar 47*78e2bd10SVarun Wadekar /******************************************************************************* 48*78e2bd10SVarun Wadekar * Static variables 49*78e2bd10SVarun Wadekar ******************************************************************************/ 50*78e2bd10SVarun Wadekar static uint64_t ns_fiq_handler_addr; 51*78e2bd10SVarun Wadekar static unsigned int fiq_handler_active; 52*78e2bd10SVarun Wadekar static pcpu_fiq_state_t fiq_state[PLATFORM_CORE_COUNT]; 53*78e2bd10SVarun Wadekar 54*78e2bd10SVarun Wadekar /******************************************************************************* 55*78e2bd10SVarun Wadekar * Handler for FIQ interrupts 56*78e2bd10SVarun Wadekar ******************************************************************************/ 57*78e2bd10SVarun Wadekar static uint64_t tegra_fiq_interrupt_handler(uint32_t id, 58*78e2bd10SVarun Wadekar uint32_t flags, 59*78e2bd10SVarun Wadekar void *handle, 60*78e2bd10SVarun Wadekar void *cookie) 61*78e2bd10SVarun Wadekar { 62*78e2bd10SVarun Wadekar cpu_context_t *ctx = cm_get_context(NON_SECURE); 63*78e2bd10SVarun Wadekar el3_state_t *el3state_ctx = get_el3state_ctx(ctx); 64*78e2bd10SVarun Wadekar int cpu = plat_my_core_pos(); 65*78e2bd10SVarun Wadekar uint32_t irq; 66*78e2bd10SVarun Wadekar 67*78e2bd10SVarun Wadekar bakery_lock_get(&tegra_fiq_lock); 68*78e2bd10SVarun Wadekar 69*78e2bd10SVarun Wadekar /* 70*78e2bd10SVarun Wadekar * The FIQ was generated when the execution was in the non-secure 71*78e2bd10SVarun Wadekar * world. Save the context registers to start with. 72*78e2bd10SVarun Wadekar */ 73*78e2bd10SVarun Wadekar cm_el1_sysregs_context_save(NON_SECURE); 74*78e2bd10SVarun Wadekar 75*78e2bd10SVarun Wadekar /* 76*78e2bd10SVarun Wadekar * Save elr_el3 and spsr_el3 from the saved context, and overwrite 77*78e2bd10SVarun Wadekar * the context with the NS fiq_handler_addr and SPSR value. 78*78e2bd10SVarun Wadekar */ 79*78e2bd10SVarun Wadekar fiq_state[cpu].elr_el3 = read_ctx_reg(el3state_ctx, CTX_ELR_EL3); 80*78e2bd10SVarun Wadekar fiq_state[cpu].spsr_el3 = read_ctx_reg(el3state_ctx, CTX_SPSR_EL3); 81*78e2bd10SVarun Wadekar 82*78e2bd10SVarun Wadekar /* 83*78e2bd10SVarun Wadekar * Set the new ELR to continue execution in the NS world using the 84*78e2bd10SVarun Wadekar * FIQ handler registered earlier. 85*78e2bd10SVarun Wadekar */ 86*78e2bd10SVarun Wadekar assert(ns_fiq_handler_addr); 87*78e2bd10SVarun Wadekar write_ctx_reg(el3state_ctx, CTX_ELR_EL3, ns_fiq_handler_addr); 88*78e2bd10SVarun Wadekar 89*78e2bd10SVarun Wadekar /* 90*78e2bd10SVarun Wadekar * Mark this interrupt as complete to avoid a FIQ storm. 91*78e2bd10SVarun Wadekar */ 92*78e2bd10SVarun Wadekar irq = plat_ic_acknowledge_interrupt(); 93*78e2bd10SVarun Wadekar if (irq < 1022) 94*78e2bd10SVarun Wadekar plat_ic_end_of_interrupt(irq); 95*78e2bd10SVarun Wadekar 96*78e2bd10SVarun Wadekar bakery_lock_release(&tegra_fiq_lock); 97*78e2bd10SVarun Wadekar 98*78e2bd10SVarun Wadekar return 0; 99*78e2bd10SVarun Wadekar } 100*78e2bd10SVarun Wadekar 101*78e2bd10SVarun Wadekar /******************************************************************************* 102*78e2bd10SVarun Wadekar * Setup handler for FIQ interrupts 103*78e2bd10SVarun Wadekar ******************************************************************************/ 104*78e2bd10SVarun Wadekar void tegra_fiq_handler_setup(void) 105*78e2bd10SVarun Wadekar { 106*78e2bd10SVarun Wadekar uint64_t flags; 107*78e2bd10SVarun Wadekar int rc; 108*78e2bd10SVarun Wadekar 109*78e2bd10SVarun Wadekar /* return if already registered */ 110*78e2bd10SVarun Wadekar if (fiq_handler_active) 111*78e2bd10SVarun Wadekar return; 112*78e2bd10SVarun Wadekar 113*78e2bd10SVarun Wadekar /* 114*78e2bd10SVarun Wadekar * Register an interrupt handler for FIQ interrupts generated for 115*78e2bd10SVarun Wadekar * NS interrupt sources 116*78e2bd10SVarun Wadekar */ 117*78e2bd10SVarun Wadekar flags = 0; 118*78e2bd10SVarun Wadekar set_interrupt_rm_flag(flags, NON_SECURE); 119*78e2bd10SVarun Wadekar rc = register_interrupt_type_handler(INTR_TYPE_S_EL1, 120*78e2bd10SVarun Wadekar tegra_fiq_interrupt_handler, 121*78e2bd10SVarun Wadekar flags); 122*78e2bd10SVarun Wadekar if (rc) 123*78e2bd10SVarun Wadekar panic(); 124*78e2bd10SVarun Wadekar 125*78e2bd10SVarun Wadekar /* handler is now active */ 126*78e2bd10SVarun Wadekar fiq_handler_active = 1; 127*78e2bd10SVarun Wadekar } 128*78e2bd10SVarun Wadekar 129*78e2bd10SVarun Wadekar /******************************************************************************* 130*78e2bd10SVarun Wadekar * Validate and store NS world's entrypoint for FIQ interrupts 131*78e2bd10SVarun Wadekar ******************************************************************************/ 132*78e2bd10SVarun Wadekar void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint) 133*78e2bd10SVarun Wadekar { 134*78e2bd10SVarun Wadekar ns_fiq_handler_addr = entrypoint; 135*78e2bd10SVarun Wadekar } 136*78e2bd10SVarun Wadekar 137*78e2bd10SVarun Wadekar /******************************************************************************* 138*78e2bd10SVarun Wadekar * Handler to return the NS EL1/EL0 CPU context 139*78e2bd10SVarun Wadekar ******************************************************************************/ 140*78e2bd10SVarun Wadekar int tegra_fiq_get_intr_context(void) 141*78e2bd10SVarun Wadekar { 142*78e2bd10SVarun Wadekar cpu_context_t *ctx = cm_get_context(NON_SECURE); 143*78e2bd10SVarun Wadekar gp_regs_t *gpregs_ctx = get_gpregs_ctx(ctx); 144*78e2bd10SVarun Wadekar el1_sys_regs_t *el1state_ctx = get_sysregs_ctx(ctx); 145*78e2bd10SVarun Wadekar int cpu = plat_my_core_pos(); 146*78e2bd10SVarun Wadekar uint64_t val; 147*78e2bd10SVarun Wadekar 148*78e2bd10SVarun Wadekar /* 149*78e2bd10SVarun Wadekar * We store the ELR_EL3, SPSR_EL3, SP_EL0 and SP_EL1 registers so 150*78e2bd10SVarun Wadekar * that el3_exit() sends these values back to the NS world. 151*78e2bd10SVarun Wadekar */ 152*78e2bd10SVarun Wadekar write_ctx_reg(gpregs_ctx, CTX_GPREG_X0, fiq_state[cpu].elr_el3); 153*78e2bd10SVarun Wadekar write_ctx_reg(gpregs_ctx, CTX_GPREG_X1, fiq_state[cpu].spsr_el3); 154*78e2bd10SVarun Wadekar 155*78e2bd10SVarun Wadekar val = read_ctx_reg(gpregs_ctx, CTX_GPREG_SP_EL0); 156*78e2bd10SVarun Wadekar write_ctx_reg(gpregs_ctx, CTX_GPREG_X2, val); 157*78e2bd10SVarun Wadekar 158*78e2bd10SVarun Wadekar val = read_ctx_reg(el1state_ctx, CTX_SP_EL1); 159*78e2bd10SVarun Wadekar write_ctx_reg(gpregs_ctx, CTX_GPREG_X3, val); 160*78e2bd10SVarun Wadekar 161*78e2bd10SVarun Wadekar return 0; 162*78e2bd10SVarun Wadekar } 163