178e2bd10SVarun Wadekar /* 278e2bd10SVarun Wadekar * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 378e2bd10SVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 578e2bd10SVarun Wadekar */ 678e2bd10SVarun Wadekar 778e2bd10SVarun Wadekar #include <arch_helpers.h> 878e2bd10SVarun Wadekar #include <assert.h> 978e2bd10SVarun Wadekar #include <bakery_lock.h> 1078e2bd10SVarun Wadekar #include <bl_common.h> 1178e2bd10SVarun Wadekar #include <context.h> 1278e2bd10SVarun Wadekar #include <context_mgmt.h> 1378e2bd10SVarun Wadekar #include <debug.h> 1478e2bd10SVarun Wadekar #include <denver.h> 1578e2bd10SVarun Wadekar #include <gic_v2.h> 1678e2bd10SVarun Wadekar #include <interrupt_mgmt.h> 1778e2bd10SVarun Wadekar #include <platform.h> 1878e2bd10SVarun Wadekar #include <tegra_def.h> 1978e2bd10SVarun Wadekar #include <tegra_private.h> 2078e2bd10SVarun Wadekar 21*5bd1a177SAnthony Zhou static DEFINE_BAKERY_LOCK(tegra_fiq_lock); 2278e2bd10SVarun Wadekar 2378e2bd10SVarun Wadekar /******************************************************************************* 2478e2bd10SVarun Wadekar * Static variables 2578e2bd10SVarun Wadekar ******************************************************************************/ 2678e2bd10SVarun Wadekar static uint64_t ns_fiq_handler_addr; 27*5bd1a177SAnthony Zhou static uint32_t fiq_handler_active; 2878e2bd10SVarun Wadekar static pcpu_fiq_state_t fiq_state[PLATFORM_CORE_COUNT]; 2978e2bd10SVarun Wadekar 3078e2bd10SVarun Wadekar /******************************************************************************* 3178e2bd10SVarun Wadekar * Handler for FIQ interrupts 3278e2bd10SVarun Wadekar ******************************************************************************/ 3378e2bd10SVarun Wadekar static uint64_t tegra_fiq_interrupt_handler(uint32_t id, 3478e2bd10SVarun Wadekar uint32_t flags, 3578e2bd10SVarun Wadekar void *handle, 3678e2bd10SVarun Wadekar void *cookie) 3778e2bd10SVarun Wadekar { 3878e2bd10SVarun Wadekar cpu_context_t *ctx = cm_get_context(NON_SECURE); 3978e2bd10SVarun Wadekar el3_state_t *el3state_ctx = get_el3state_ctx(ctx); 40*5bd1a177SAnthony Zhou uint32_t cpu = plat_my_core_pos(); 4178e2bd10SVarun Wadekar uint32_t irq; 4278e2bd10SVarun Wadekar 4378e2bd10SVarun Wadekar bakery_lock_get(&tegra_fiq_lock); 4478e2bd10SVarun Wadekar 4578e2bd10SVarun Wadekar /* 4678e2bd10SVarun Wadekar * The FIQ was generated when the execution was in the non-secure 4778e2bd10SVarun Wadekar * world. Save the context registers to start with. 4878e2bd10SVarun Wadekar */ 4978e2bd10SVarun Wadekar cm_el1_sysregs_context_save(NON_SECURE); 5078e2bd10SVarun Wadekar 5178e2bd10SVarun Wadekar /* 5278e2bd10SVarun Wadekar * Save elr_el3 and spsr_el3 from the saved context, and overwrite 5378e2bd10SVarun Wadekar * the context with the NS fiq_handler_addr and SPSR value. 5478e2bd10SVarun Wadekar */ 55*5bd1a177SAnthony Zhou fiq_state[cpu].elr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3)); 56*5bd1a177SAnthony Zhou fiq_state[cpu].spsr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_SPSR_EL3)); 5778e2bd10SVarun Wadekar 5878e2bd10SVarun Wadekar /* 5978e2bd10SVarun Wadekar * Set the new ELR to continue execution in the NS world using the 6078e2bd10SVarun Wadekar * FIQ handler registered earlier. 6178e2bd10SVarun Wadekar */ 6278e2bd10SVarun Wadekar assert(ns_fiq_handler_addr); 63*5bd1a177SAnthony Zhou write_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3), (ns_fiq_handler_addr)); 6478e2bd10SVarun Wadekar 6578e2bd10SVarun Wadekar /* 6678e2bd10SVarun Wadekar * Mark this interrupt as complete to avoid a FIQ storm. 6778e2bd10SVarun Wadekar */ 6878e2bd10SVarun Wadekar irq = plat_ic_acknowledge_interrupt(); 69*5bd1a177SAnthony Zhou if (irq < 1022U) { 7078e2bd10SVarun Wadekar plat_ic_end_of_interrupt(irq); 71*5bd1a177SAnthony Zhou } 7278e2bd10SVarun Wadekar 7378e2bd10SVarun Wadekar bakery_lock_release(&tegra_fiq_lock); 7478e2bd10SVarun Wadekar 7578e2bd10SVarun Wadekar return 0; 7678e2bd10SVarun Wadekar } 7778e2bd10SVarun Wadekar 7878e2bd10SVarun Wadekar /******************************************************************************* 7978e2bd10SVarun Wadekar * Setup handler for FIQ interrupts 8078e2bd10SVarun Wadekar ******************************************************************************/ 8178e2bd10SVarun Wadekar void tegra_fiq_handler_setup(void) 8278e2bd10SVarun Wadekar { 83*5bd1a177SAnthony Zhou uint32_t flags; 84*5bd1a177SAnthony Zhou int32_t rc; 8578e2bd10SVarun Wadekar 8678e2bd10SVarun Wadekar /* return if already registered */ 87*5bd1a177SAnthony Zhou if (fiq_handler_active == 0U) { 8878e2bd10SVarun Wadekar /* 8978e2bd10SVarun Wadekar * Register an interrupt handler for FIQ interrupts generated for 9078e2bd10SVarun Wadekar * NS interrupt sources 9178e2bd10SVarun Wadekar */ 92*5bd1a177SAnthony Zhou flags = 0U; 93*5bd1a177SAnthony Zhou set_interrupt_rm_flag((flags), (NON_SECURE)); 9445eab456SVarun Wadekar rc = register_interrupt_type_handler(INTR_TYPE_EL3, 9578e2bd10SVarun Wadekar tegra_fiq_interrupt_handler, 9678e2bd10SVarun Wadekar flags); 97*5bd1a177SAnthony Zhou if (rc != 0) { 9878e2bd10SVarun Wadekar panic(); 99*5bd1a177SAnthony Zhou } 10078e2bd10SVarun Wadekar 10178e2bd10SVarun Wadekar /* handler is now active */ 10278e2bd10SVarun Wadekar fiq_handler_active = 1; 10378e2bd10SVarun Wadekar } 104*5bd1a177SAnthony Zhou } 10578e2bd10SVarun Wadekar 10678e2bd10SVarun Wadekar /******************************************************************************* 10778e2bd10SVarun Wadekar * Validate and store NS world's entrypoint for FIQ interrupts 10878e2bd10SVarun Wadekar ******************************************************************************/ 10978e2bd10SVarun Wadekar void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint) 11078e2bd10SVarun Wadekar { 11178e2bd10SVarun Wadekar ns_fiq_handler_addr = entrypoint; 11278e2bd10SVarun Wadekar } 11378e2bd10SVarun Wadekar 11478e2bd10SVarun Wadekar /******************************************************************************* 11578e2bd10SVarun Wadekar * Handler to return the NS EL1/EL0 CPU context 11678e2bd10SVarun Wadekar ******************************************************************************/ 117*5bd1a177SAnthony Zhou int32_t tegra_fiq_get_intr_context(void) 11878e2bd10SVarun Wadekar { 11978e2bd10SVarun Wadekar cpu_context_t *ctx = cm_get_context(NON_SECURE); 12078e2bd10SVarun Wadekar gp_regs_t *gpregs_ctx = get_gpregs_ctx(ctx); 121*5bd1a177SAnthony Zhou const el1_sys_regs_t *el1state_ctx = get_sysregs_ctx(ctx); 122*5bd1a177SAnthony Zhou uint32_t cpu = plat_my_core_pos(); 12378e2bd10SVarun Wadekar uint64_t val; 12478e2bd10SVarun Wadekar 12578e2bd10SVarun Wadekar /* 12678e2bd10SVarun Wadekar * We store the ELR_EL3, SPSR_EL3, SP_EL0 and SP_EL1 registers so 12778e2bd10SVarun Wadekar * that el3_exit() sends these values back to the NS world. 12878e2bd10SVarun Wadekar */ 129*5bd1a177SAnthony Zhou write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X0), (fiq_state[cpu].elr_el3)); 130*5bd1a177SAnthony Zhou write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X1), (fiq_state[cpu].spsr_el3)); 13178e2bd10SVarun Wadekar 132*5bd1a177SAnthony Zhou val = read_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_SP_EL0)); 133*5bd1a177SAnthony Zhou write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X2), (val)); 13478e2bd10SVarun Wadekar 135*5bd1a177SAnthony Zhou val = read_ctx_reg((el1state_ctx), (uint32_t)(CTX_SP_EL1)); 136*5bd1a177SAnthony Zhou write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X3), (val)); 13778e2bd10SVarun Wadekar 13878e2bd10SVarun Wadekar return 0; 13978e2bd10SVarun Wadekar } 140