178e2bd10SVarun Wadekar /* 278e2bd10SVarun Wadekar * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 378e2bd10SVarun Wadekar * 478e2bd10SVarun Wadekar * Redistribution and use in source and binary forms, with or without 578e2bd10SVarun Wadekar * modification, are permitted provided that the following conditions are met: 678e2bd10SVarun Wadekar * 778e2bd10SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 878e2bd10SVarun Wadekar * list of conditions and the following disclaimer. 978e2bd10SVarun Wadekar * 1078e2bd10SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 1178e2bd10SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 1278e2bd10SVarun Wadekar * and/or other materials provided with the distribution. 1378e2bd10SVarun Wadekar * 1478e2bd10SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 1578e2bd10SVarun Wadekar * to endorse or promote products derived from this software without specific 1678e2bd10SVarun Wadekar * prior written permission. 1778e2bd10SVarun Wadekar * 1878e2bd10SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 1978e2bd10SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2078e2bd10SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2178e2bd10SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2278e2bd10SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2378e2bd10SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2478e2bd10SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2578e2bd10SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2678e2bd10SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2778e2bd10SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 2878e2bd10SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 2978e2bd10SVarun Wadekar */ 3078e2bd10SVarun Wadekar 3178e2bd10SVarun Wadekar #include <arch_helpers.h> 3278e2bd10SVarun Wadekar #include <assert.h> 3378e2bd10SVarun Wadekar #include <bakery_lock.h> 3478e2bd10SVarun Wadekar #include <bl_common.h> 3578e2bd10SVarun Wadekar #include <context.h> 3678e2bd10SVarun Wadekar #include <context_mgmt.h> 3778e2bd10SVarun Wadekar #include <debug.h> 3878e2bd10SVarun Wadekar #include <denver.h> 3978e2bd10SVarun Wadekar #include <gic_v2.h> 4078e2bd10SVarun Wadekar #include <interrupt_mgmt.h> 4178e2bd10SVarun Wadekar #include <platform.h> 4278e2bd10SVarun Wadekar #include <tegra_def.h> 4378e2bd10SVarun Wadekar #include <tegra_private.h> 4478e2bd10SVarun Wadekar 4578e2bd10SVarun Wadekar DEFINE_BAKERY_LOCK(tegra_fiq_lock); 4678e2bd10SVarun Wadekar 4778e2bd10SVarun Wadekar /******************************************************************************* 4878e2bd10SVarun Wadekar * Static variables 4978e2bd10SVarun Wadekar ******************************************************************************/ 5078e2bd10SVarun Wadekar static uint64_t ns_fiq_handler_addr; 5178e2bd10SVarun Wadekar static unsigned int fiq_handler_active; 5278e2bd10SVarun Wadekar static pcpu_fiq_state_t fiq_state[PLATFORM_CORE_COUNT]; 5378e2bd10SVarun Wadekar 5478e2bd10SVarun Wadekar /******************************************************************************* 5578e2bd10SVarun Wadekar * Handler for FIQ interrupts 5678e2bd10SVarun Wadekar ******************************************************************************/ 5778e2bd10SVarun Wadekar static uint64_t tegra_fiq_interrupt_handler(uint32_t id, 5878e2bd10SVarun Wadekar uint32_t flags, 5978e2bd10SVarun Wadekar void *handle, 6078e2bd10SVarun Wadekar void *cookie) 6178e2bd10SVarun Wadekar { 6278e2bd10SVarun Wadekar cpu_context_t *ctx = cm_get_context(NON_SECURE); 6378e2bd10SVarun Wadekar el3_state_t *el3state_ctx = get_el3state_ctx(ctx); 6478e2bd10SVarun Wadekar int cpu = plat_my_core_pos(); 6578e2bd10SVarun Wadekar uint32_t irq; 6678e2bd10SVarun Wadekar 6778e2bd10SVarun Wadekar bakery_lock_get(&tegra_fiq_lock); 6878e2bd10SVarun Wadekar 6978e2bd10SVarun Wadekar /* 7078e2bd10SVarun Wadekar * The FIQ was generated when the execution was in the non-secure 7178e2bd10SVarun Wadekar * world. Save the context registers to start with. 7278e2bd10SVarun Wadekar */ 7378e2bd10SVarun Wadekar cm_el1_sysregs_context_save(NON_SECURE); 7478e2bd10SVarun Wadekar 7578e2bd10SVarun Wadekar /* 7678e2bd10SVarun Wadekar * Save elr_el3 and spsr_el3 from the saved context, and overwrite 7778e2bd10SVarun Wadekar * the context with the NS fiq_handler_addr and SPSR value. 7878e2bd10SVarun Wadekar */ 7978e2bd10SVarun Wadekar fiq_state[cpu].elr_el3 = read_ctx_reg(el3state_ctx, CTX_ELR_EL3); 8078e2bd10SVarun Wadekar fiq_state[cpu].spsr_el3 = read_ctx_reg(el3state_ctx, CTX_SPSR_EL3); 8178e2bd10SVarun Wadekar 8278e2bd10SVarun Wadekar /* 8378e2bd10SVarun Wadekar * Set the new ELR to continue execution in the NS world using the 8478e2bd10SVarun Wadekar * FIQ handler registered earlier. 8578e2bd10SVarun Wadekar */ 8678e2bd10SVarun Wadekar assert(ns_fiq_handler_addr); 8778e2bd10SVarun Wadekar write_ctx_reg(el3state_ctx, CTX_ELR_EL3, ns_fiq_handler_addr); 8878e2bd10SVarun Wadekar 8978e2bd10SVarun Wadekar /* 9078e2bd10SVarun Wadekar * Mark this interrupt as complete to avoid a FIQ storm. 9178e2bd10SVarun Wadekar */ 9278e2bd10SVarun Wadekar irq = plat_ic_acknowledge_interrupt(); 9378e2bd10SVarun Wadekar if (irq < 1022) 9478e2bd10SVarun Wadekar plat_ic_end_of_interrupt(irq); 9578e2bd10SVarun Wadekar 9678e2bd10SVarun Wadekar bakery_lock_release(&tegra_fiq_lock); 9778e2bd10SVarun Wadekar 9878e2bd10SVarun Wadekar return 0; 9978e2bd10SVarun Wadekar } 10078e2bd10SVarun Wadekar 10178e2bd10SVarun Wadekar /******************************************************************************* 10278e2bd10SVarun Wadekar * Setup handler for FIQ interrupts 10378e2bd10SVarun Wadekar ******************************************************************************/ 10478e2bd10SVarun Wadekar void tegra_fiq_handler_setup(void) 10578e2bd10SVarun Wadekar { 10678e2bd10SVarun Wadekar uint64_t flags; 10778e2bd10SVarun Wadekar int rc; 10878e2bd10SVarun Wadekar 10978e2bd10SVarun Wadekar /* return if already registered */ 11078e2bd10SVarun Wadekar if (fiq_handler_active) 11178e2bd10SVarun Wadekar return; 11278e2bd10SVarun Wadekar 11378e2bd10SVarun Wadekar /* 11478e2bd10SVarun Wadekar * Register an interrupt handler for FIQ interrupts generated for 11578e2bd10SVarun Wadekar * NS interrupt sources 11678e2bd10SVarun Wadekar */ 11778e2bd10SVarun Wadekar flags = 0; 11878e2bd10SVarun Wadekar set_interrupt_rm_flag(flags, NON_SECURE); 119*45eab456SVarun Wadekar rc = register_interrupt_type_handler(INTR_TYPE_EL3, 12078e2bd10SVarun Wadekar tegra_fiq_interrupt_handler, 12178e2bd10SVarun Wadekar flags); 12278e2bd10SVarun Wadekar if (rc) 12378e2bd10SVarun Wadekar panic(); 12478e2bd10SVarun Wadekar 12578e2bd10SVarun Wadekar /* handler is now active */ 12678e2bd10SVarun Wadekar fiq_handler_active = 1; 12778e2bd10SVarun Wadekar } 12878e2bd10SVarun Wadekar 12978e2bd10SVarun Wadekar /******************************************************************************* 13078e2bd10SVarun Wadekar * Validate and store NS world's entrypoint for FIQ interrupts 13178e2bd10SVarun Wadekar ******************************************************************************/ 13278e2bd10SVarun Wadekar void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint) 13378e2bd10SVarun Wadekar { 13478e2bd10SVarun Wadekar ns_fiq_handler_addr = entrypoint; 13578e2bd10SVarun Wadekar } 13678e2bd10SVarun Wadekar 13778e2bd10SVarun Wadekar /******************************************************************************* 13878e2bd10SVarun Wadekar * Handler to return the NS EL1/EL0 CPU context 13978e2bd10SVarun Wadekar ******************************************************************************/ 14078e2bd10SVarun Wadekar int tegra_fiq_get_intr_context(void) 14178e2bd10SVarun Wadekar { 14278e2bd10SVarun Wadekar cpu_context_t *ctx = cm_get_context(NON_SECURE); 14378e2bd10SVarun Wadekar gp_regs_t *gpregs_ctx = get_gpregs_ctx(ctx); 14478e2bd10SVarun Wadekar el1_sys_regs_t *el1state_ctx = get_sysregs_ctx(ctx); 14578e2bd10SVarun Wadekar int cpu = plat_my_core_pos(); 14678e2bd10SVarun Wadekar uint64_t val; 14778e2bd10SVarun Wadekar 14878e2bd10SVarun Wadekar /* 14978e2bd10SVarun Wadekar * We store the ELR_EL3, SPSR_EL3, SP_EL0 and SP_EL1 registers so 15078e2bd10SVarun Wadekar * that el3_exit() sends these values back to the NS world. 15178e2bd10SVarun Wadekar */ 15278e2bd10SVarun Wadekar write_ctx_reg(gpregs_ctx, CTX_GPREG_X0, fiq_state[cpu].elr_el3); 15378e2bd10SVarun Wadekar write_ctx_reg(gpregs_ctx, CTX_GPREG_X1, fiq_state[cpu].spsr_el3); 15478e2bd10SVarun Wadekar 15578e2bd10SVarun Wadekar val = read_ctx_reg(gpregs_ctx, CTX_GPREG_SP_EL0); 15678e2bd10SVarun Wadekar write_ctx_reg(gpregs_ctx, CTX_GPREG_X2, val); 15778e2bd10SVarun Wadekar 15878e2bd10SVarun Wadekar val = read_ctx_reg(el1state_ctx, CTX_SP_EL1); 15978e2bd10SVarun Wadekar write_ctx_reg(gpregs_ctx, CTX_GPREG_X3, val); 16078e2bd10SVarun Wadekar 16178e2bd10SVarun Wadekar return 0; 16278e2bd10SVarun Wadekar } 163