1*c8961326SVarun Wadekar /* 2*c8961326SVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3*c8961326SVarun Wadekar * 4*c8961326SVarun Wadekar * Redistribution and use in source and binary forms, with or without 5*c8961326SVarun Wadekar * modification, are permitted provided that the following conditions are met: 6*c8961326SVarun Wadekar * 7*c8961326SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 8*c8961326SVarun Wadekar * list of conditions and the following disclaimer. 9*c8961326SVarun Wadekar * 10*c8961326SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 11*c8961326SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 12*c8961326SVarun Wadekar * and/or other materials provided with the distribution. 13*c8961326SVarun Wadekar * 14*c8961326SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 15*c8961326SVarun Wadekar * to endorse or promote products derived from this software without specific 16*c8961326SVarun Wadekar * prior written permission. 17*c8961326SVarun Wadekar * 18*c8961326SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*c8961326SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*c8961326SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*c8961326SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*c8961326SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*c8961326SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*c8961326SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*c8961326SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*c8961326SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*c8961326SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*c8961326SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 29*c8961326SVarun Wadekar */ 30*c8961326SVarun Wadekar 31*c8961326SVarun Wadekar #include <delay_timer.h> 32*c8961326SVarun Wadekar #include <mmio.h> 33*c8961326SVarun Wadekar #include <tegra_def.h> 34*c8961326SVarun Wadekar 35*c8961326SVarun Wadekar static uint32_t tegra_timerus_get_value(void) 36*c8961326SVarun Wadekar { 37*c8961326SVarun Wadekar return mmio_read_32(TEGRA_TMRUS_BASE); 38*c8961326SVarun Wadekar } 39*c8961326SVarun Wadekar 40*c8961326SVarun Wadekar static const timer_ops_t tegra_timer_ops = { 41*c8961326SVarun Wadekar .get_timer_value = tegra_timerus_get_value, 42*c8961326SVarun Wadekar .clk_mult = 1, 43*c8961326SVarun Wadekar .clk_div = 1, 44*c8961326SVarun Wadekar }; 45*c8961326SVarun Wadekar 46*c8961326SVarun Wadekar /* 47*c8961326SVarun Wadekar * Initialise the on-chip free rolling us counter as the delay 48*c8961326SVarun Wadekar * timer. 49*c8961326SVarun Wadekar */ 50*c8961326SVarun Wadekar void tegra_delay_timer_init(void) 51*c8961326SVarun Wadekar { 52*c8961326SVarun Wadekar timer_init(&tegra_timer_ops); 53*c8961326SVarun Wadekar } 54