1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <bl31.h> 11 #include <bl_common.h> 12 #include <console.h> 13 #include <cortex_a53.h> 14 #include <cortex_a57.h> 15 #include <debug.h> 16 #include <denver.h> 17 #include <errno.h> 18 #include <memctrl.h> 19 #include <mmio.h> 20 #include <platform.h> 21 #include <platform_def.h> 22 #include <stddef.h> 23 #include <string.h> 24 #include <tegra_def.h> 25 #include <tegra_private.h> 26 #include <utils_def.h> 27 28 /* length of Trusty's input parameters (in bytes) */ 29 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 30 31 extern void memcpy16(void *dest, const void *src, unsigned int length); 32 extern void zeromem16(void *mem, unsigned int length); 33 34 /******************************************************************************* 35 * Declarations of linker defined symbols which will help us find the layout 36 * of trusted SRAM 37 ******************************************************************************/ 38 39 IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START); 40 IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END); 41 IMPORT_SYM(unsigned long, __RODATA_START__, BL31_RODATA_BASE); 42 IMPORT_SYM(unsigned long, __RODATA_END__, BL31_RODATA_END); 43 IMPORT_SYM(unsigned long, __TEXT_START__, TEXT_START); 44 IMPORT_SYM(unsigned long, __TEXT_END__, TEXT_END); 45 46 extern uint64_t tegra_bl31_phys_base; 47 extern uint64_t tegra_console_base; 48 49 50 static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; 51 static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { 52 .tzdram_size = (uint64_t)TZDRAM_SIZE 53 }; 54 static unsigned long bl32_mem_size; 55 static unsigned long bl32_boot_params; 56 57 /******************************************************************************* 58 * This variable holds the non-secure image entry address 59 ******************************************************************************/ 60 extern uint64_t ns_image_entrypoint; 61 62 /******************************************************************************* 63 * The following platform setup functions are weakly defined. They 64 * provide typical implementations that will be overridden by a SoC. 65 ******************************************************************************/ 66 #pragma weak plat_early_platform_setup 67 #pragma weak plat_get_bl31_params 68 #pragma weak plat_get_bl31_plat_params 69 70 void plat_early_platform_setup(void) 71 { 72 ; /* do nothing */ 73 } 74 75 bl31_params_t *plat_get_bl31_params(void) 76 { 77 return NULL; 78 } 79 80 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 81 { 82 return NULL; 83 } 84 85 /******************************************************************************* 86 * Return a pointer to the 'entry_point_info' structure of the next image for 87 * security state specified. BL33 corresponds to the non-secure image type 88 * while BL32 corresponds to the secure image type. 89 ******************************************************************************/ 90 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 91 { 92 if (type == NON_SECURE) 93 return &bl33_image_ep_info; 94 95 /* return BL32 entry point info if it is valid */ 96 if (type == SECURE && bl32_image_ep_info.pc) 97 return &bl32_image_ep_info; 98 99 return NULL; 100 } 101 102 /******************************************************************************* 103 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image 104 * passes this platform specific information. 105 ******************************************************************************/ 106 plat_params_from_bl2_t *bl31_get_plat_params(void) 107 { 108 return &plat_bl31_params_from_bl2; 109 } 110 111 /******************************************************************************* 112 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image 113 * info. 114 ******************************************************************************/ 115 void bl31_early_platform_setup(bl31_params_t *from_bl2, 116 void *plat_params_from_bl2) 117 { 118 plat_params_from_bl2_t *plat_params = 119 (plat_params_from_bl2_t *)plat_params_from_bl2; 120 image_info_t bl32_img_info = { {0} }; 121 uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end; 122 123 /* 124 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so 125 * there's no argument to relay from a previous bootloader. Platforms 126 * might use custom ways to get arguments, so provide handlers which 127 * they can override. 128 */ 129 if (from_bl2 == NULL) 130 from_bl2 = plat_get_bl31_params(); 131 if (plat_params == NULL) 132 plat_params = plat_get_bl31_plat_params(); 133 134 /* 135 * Copy BL3-3, BL3-2 entry point information. 136 * They are stored in Secure RAM, in BL2's address space. 137 */ 138 assert(from_bl2); 139 assert(from_bl2->bl33_ep_info); 140 bl33_image_ep_info = *from_bl2->bl33_ep_info; 141 142 if (from_bl2->bl32_ep_info) { 143 bl32_image_ep_info = *from_bl2->bl32_ep_info; 144 bl32_mem_size = from_bl2->bl32_ep_info->args.arg0; 145 bl32_boot_params = from_bl2->bl32_ep_info->args.arg2; 146 } 147 148 /* 149 * Parse platform specific parameters - TZDRAM aperture base and size 150 */ 151 assert(plat_params); 152 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base; 153 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; 154 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id; 155 156 /* 157 * It is very important that we run either from TZDRAM or TZSRAM base. 158 * Add an explicit check here. 159 */ 160 if ((plat_bl31_params_from_bl2.tzdram_base != BL31_BASE) && 161 (TEGRA_TZRAM_BASE != BL31_BASE)) 162 panic(); 163 164 /* 165 * Get the base address of the UART controller to be used for the 166 * console 167 */ 168 tegra_console_base = plat_get_console_from_id(plat_params->uart_id); 169 170 if (tegra_console_base != (uint64_t)0) { 171 /* 172 * Configure the UART port to be used as the console 173 */ 174 console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ, 175 TEGRA_CONSOLE_BAUDRATE); 176 } 177 178 /* 179 * Initialize delay timer 180 */ 181 tegra_delay_timer_init(); 182 183 /* 184 * Do initial security configuration to allow DRAM/device access. 185 */ 186 tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base, 187 plat_bl31_params_from_bl2.tzdram_size); 188 189 /* 190 * The previous bootloader might not have placed the BL32 image 191 * inside the TZDRAM. We check the BL32 image info to find out 192 * the base/PC values and relocate the image if necessary. 193 */ 194 if (from_bl2->bl32_image_info) { 195 196 bl32_img_info = *from_bl2->bl32_image_info; 197 198 /* Relocate BL32 if it resides outside of the TZDRAM */ 199 tzdram_start = plat_bl31_params_from_bl2.tzdram_base; 200 tzdram_end = plat_bl31_params_from_bl2.tzdram_base + 201 plat_bl31_params_from_bl2.tzdram_size; 202 bl32_start = bl32_img_info.image_base; 203 bl32_end = bl32_img_info.image_base + bl32_img_info.image_size; 204 205 assert(tzdram_end > tzdram_start); 206 assert(bl32_end > bl32_start); 207 assert(bl32_image_ep_info.pc > tzdram_start); 208 assert(bl32_image_ep_info.pc < tzdram_end); 209 210 /* relocate BL32 */ 211 if (bl32_start >= tzdram_end || bl32_end <= tzdram_start) { 212 213 INFO("Relocate BL32 to TZDRAM\n"); 214 215 memcpy16((void *)(uintptr_t)bl32_image_ep_info.pc, 216 (void *)(uintptr_t)bl32_start, 217 bl32_img_info.image_size); 218 219 /* clean up non-secure intermediate buffer */ 220 zeromem16((void *)(uintptr_t)bl32_start, 221 bl32_img_info.image_size); 222 } 223 } 224 225 /* Early platform setup for Tegra SoCs */ 226 plat_early_platform_setup(); 227 228 INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", 229 (((read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK) 230 == DENVER_IMPL) ? "Denver" : "ARM", read_mpidr()); 231 } 232 233 #ifdef SPD_trusty 234 void plat_trusty_set_boot_args(aapcs64_params_t *args) 235 { 236 args->arg0 = bl32_mem_size; 237 args->arg1 = bl32_boot_params; 238 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 239 } 240 #endif 241 242 /******************************************************************************* 243 * Initialize the gic, configure the SCR. 244 ******************************************************************************/ 245 void bl31_platform_setup(void) 246 { 247 uint32_t tmp_reg; 248 249 /* Initialize the gic cpu and distributor interfaces */ 250 plat_gic_setup(); 251 252 /* 253 * Setup secondary CPU POR infrastructure. 254 */ 255 plat_secondary_setup(); 256 257 /* 258 * Initial Memory Controller configuration. 259 */ 260 tegra_memctrl_setup(); 261 262 /* 263 * Set up the TZRAM memory aperture to allow only secure world 264 * access 265 */ 266 tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE); 267 268 /* Set the next EL to be AArch64 */ 269 tmp_reg = SCR_RES1_BITS | SCR_RW_BIT; 270 write_scr(tmp_reg); 271 272 INFO("BL3-1: Tegra platform setup complete\n"); 273 } 274 275 /******************************************************************************* 276 * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit 277 ******************************************************************************/ 278 void bl31_plat_runtime_setup(void) 279 { 280 /* 281 * During boot, USB3 and flash media (SDMMC/SATA) devices need 282 * access to IRAM. Because these clients connect to the MC and 283 * do not have a direct path to the IRAM, the MC implements AHB 284 * redirection during boot to allow path to IRAM. In this mode 285 * accesses to a programmed memory address aperture are directed 286 * to the AHB bus, allowing access to the IRAM. This mode must be 287 * disabled before we jump to the non-secure world. 288 */ 289 tegra_memctrl_disable_ahb_redirection(); 290 } 291 292 /******************************************************************************* 293 * Perform the very early platform specific architectural setup here. At the 294 * moment this only intializes the mmu in a quick and dirty way. 295 ******************************************************************************/ 296 void bl31_plat_arch_setup(void) 297 { 298 unsigned long rw_start = BL31_RW_START; 299 unsigned long rw_size = BL31_RW_END - BL31_RW_START; 300 unsigned long rodata_start = BL31_RODATA_BASE; 301 unsigned long rodata_size = BL31_RODATA_END - BL31_RODATA_BASE; 302 unsigned long code_base = TEXT_START; 303 unsigned long code_size = TEXT_END - TEXT_START; 304 const mmap_region_t *plat_mmio_map = NULL; 305 #if USE_COHERENT_MEM 306 unsigned long coh_start, coh_size; 307 #endif 308 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 309 310 /* add memory regions */ 311 mmap_add_region(rw_start, rw_start, 312 rw_size, 313 MT_MEMORY | MT_RW | MT_SECURE); 314 mmap_add_region(rodata_start, rodata_start, 315 rodata_size, 316 MT_RO_DATA | MT_SECURE); 317 mmap_add_region(code_base, code_base, 318 code_size, 319 MT_CODE | MT_SECURE); 320 321 /* map TZDRAM used by BL31 as coherent memory */ 322 if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) { 323 mmap_add_region(params_from_bl2->tzdram_base, 324 params_from_bl2->tzdram_base, 325 BL31_SIZE, 326 MT_DEVICE | MT_RW | MT_SECURE); 327 } 328 329 #if USE_COHERENT_MEM 330 coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE); 331 coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE; 332 333 mmap_add_region(coh_start, coh_start, 334 coh_size, 335 MT_DEVICE | MT_RW | MT_SECURE); 336 #endif 337 338 /* map on-chip free running uS timer */ 339 mmap_add_region(page_align((uint64_t)TEGRA_TMRUS_BASE, 0), 340 page_align((uint64_t)TEGRA_TMRUS_BASE, 0), 341 (uint64_t)TEGRA_TMRUS_SIZE, 342 MT_DEVICE | MT_RO | MT_SECURE); 343 344 /* add MMIO space */ 345 plat_mmio_map = plat_get_mmio_map(); 346 if (plat_mmio_map) 347 mmap_add(plat_mmio_map); 348 else 349 WARN("MMIO map not available\n"); 350 351 /* set up translation tables */ 352 init_xlat_tables(); 353 354 /* enable the MMU */ 355 enable_mmu_el3(0); 356 357 INFO("BL3-1: Tegra: MMU enabled\n"); 358 } 359 360 /******************************************************************************* 361 * Check if the given NS DRAM range is valid 362 ******************************************************************************/ 363 int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes) 364 { 365 uint64_t end = base + size_in_bytes; 366 367 /* 368 * Check if the NS DRAM address is valid 369 */ 370 if ((base < TEGRA_DRAM_BASE) || (end > TEGRA_DRAM_END)) { 371 ERROR("NS address is out-of-bounds!\n"); 372 return -EFAULT; 373 } 374 375 /* 376 * TZDRAM aperture contains the BL31 and BL32 images, so we need 377 * to check if the NS DRAM range overlaps the TZDRAM aperture. 378 */ 379 if ((base < TZDRAM_END) && (end > tegra_bl31_phys_base)) { 380 ERROR("NS address overlaps TZDRAM!\n"); 381 return -ENOTSUP; 382 } 383 384 /* valid NS address */ 385 return 0; 386 } 387