1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <bl31.h> 35 #include <bl_common.h> 36 #include <console.h> 37 #include <cortex_a57.h> 38 #include <cortex_a53.h> 39 #include <debug.h> 40 #include <denver.h> 41 #include <errno.h> 42 #include <memctrl.h> 43 #include <mmio.h> 44 #include <platform.h> 45 #include <platform_def.h> 46 #include <stddef.h> 47 #include <tegra_def.h> 48 #include <tegra_private.h> 49 50 /******************************************************************************* 51 * Declarations of linker defined symbols which will help us find the layout 52 * of trusted SRAM 53 ******************************************************************************/ 54 extern unsigned long __RO_START__; 55 extern unsigned long __RO_END__; 56 extern unsigned long __BL31_END__; 57 58 extern uint64_t tegra_bl31_phys_base; 59 extern uint64_t tegra_console_base; 60 61 /* 62 * The next 3 constants identify the extents of the code, RO data region and the 63 * limit of the BL3-1 image. These addresses are used by the MMU setup code and 64 * therefore they must be page-aligned. It is the responsibility of the linker 65 * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols 66 * refer to page-aligned addresses. 67 */ 68 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 69 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 70 #define BL31_END (unsigned long)(&__BL31_END__) 71 72 static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; 73 static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { 74 .tzdram_size = (uint64_t)TZDRAM_SIZE 75 }; 76 77 /******************************************************************************* 78 * This variable holds the non-secure image entry address 79 ******************************************************************************/ 80 extern uint64_t ns_image_entrypoint; 81 82 /******************************************************************************* 83 * The following platform setup functions are weakly defined. They 84 * provide typical implementations that will be overridden by a SoC. 85 ******************************************************************************/ 86 #pragma weak plat_early_platform_setup 87 #pragma weak plat_get_bl31_params 88 #pragma weak plat_get_bl31_plat_params 89 90 void plat_early_platform_setup(void) 91 { 92 ; /* do nothing */ 93 } 94 95 bl31_params_t *plat_get_bl31_params(void) 96 { 97 return NULL; 98 } 99 100 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 101 { 102 return NULL; 103 } 104 105 /******************************************************************************* 106 * Return a pointer to the 'entry_point_info' structure of the next image for 107 * security state specified. BL33 corresponds to the non-secure image type 108 * while BL32 corresponds to the secure image type. 109 ******************************************************************************/ 110 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 111 { 112 if (type == NON_SECURE) 113 return &bl33_image_ep_info; 114 115 /* return BL32 entry point info if it is valid */ 116 if (type == SECURE && bl32_image_ep_info.pc) 117 return &bl32_image_ep_info; 118 119 return NULL; 120 } 121 122 /******************************************************************************* 123 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image 124 * passes this platform specific information. 125 ******************************************************************************/ 126 plat_params_from_bl2_t *bl31_get_plat_params(void) 127 { 128 return &plat_bl31_params_from_bl2; 129 } 130 131 /******************************************************************************* 132 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image 133 * info. 134 ******************************************************************************/ 135 void bl31_early_platform_setup(bl31_params_t *from_bl2, 136 void *plat_params_from_bl2) 137 { 138 plat_params_from_bl2_t *plat_params = 139 (plat_params_from_bl2_t *)plat_params_from_bl2; 140 #if DEBUG 141 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 142 #endif 143 144 /* 145 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so 146 * there's no argument to relay from a previous bootloader. Platforms 147 * might use custom ways to get arguments, so provide handlers which 148 * they can override. 149 */ 150 if (from_bl2 == NULL) 151 from_bl2 = plat_get_bl31_params(); 152 if (plat_params == NULL) 153 plat_params = plat_get_bl31_plat_params(); 154 155 /* 156 * Copy BL3-3, BL3-2 entry point information. 157 * They are stored in Secure RAM, in BL2's address space. 158 */ 159 assert(from_bl2); 160 assert(from_bl2->bl33_ep_info); 161 bl33_image_ep_info = *from_bl2->bl33_ep_info; 162 163 if (from_bl2->bl32_ep_info) 164 bl32_image_ep_info = *from_bl2->bl32_ep_info; 165 166 /* 167 * Parse platform specific parameters - TZDRAM aperture base and size 168 */ 169 assert(plat_params); 170 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base; 171 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; 172 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id; 173 174 /* 175 * It is very important that we run either from TZDRAM or TZSRAM base. 176 * Add an explicit check here. 177 */ 178 if ((plat_bl31_params_from_bl2.tzdram_base != BL31_BASE) && 179 (TEGRA_TZRAM_BASE != BL31_BASE)) 180 panic(); 181 182 /* 183 * Get the base address of the UART controller to be used for the 184 * console 185 */ 186 assert(plat_params->uart_id); 187 tegra_console_base = plat_get_console_from_id(plat_params->uart_id); 188 189 /* 190 * Configure the UART port to be used as the console 191 */ 192 assert(tegra_console_base); 193 console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ, 194 TEGRA_CONSOLE_BAUDRATE); 195 196 /* Initialise crash console */ 197 plat_crash_console_init(); 198 199 /* 200 * Do initial security configuration to allow DRAM/device access. 201 */ 202 tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base, 203 plat_bl31_params_from_bl2.tzdram_size); 204 205 /* Early platform setup for Tegra SoCs */ 206 plat_early_platform_setup(); 207 208 INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", (impl == DENVER_IMPL) ? 209 "Denver" : "ARM", read_mpidr()); 210 } 211 212 /******************************************************************************* 213 * Initialize the gic, configure the SCR. 214 ******************************************************************************/ 215 void bl31_platform_setup(void) 216 { 217 uint32_t tmp_reg; 218 219 /* Initialize the gic cpu and distributor interfaces */ 220 plat_gic_setup(); 221 222 /* 223 * Initialize delay timer 224 */ 225 tegra_delay_timer_init(); 226 227 /* 228 * Setup secondary CPU POR infrastructure. 229 */ 230 plat_secondary_setup(); 231 232 /* 233 * Initial Memory Controller configuration. 234 */ 235 tegra_memctrl_setup(); 236 237 /* 238 * Set up the TZRAM memory aperture to allow only secure world 239 * access 240 */ 241 tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE); 242 243 /* Set the next EL to be AArch64 */ 244 tmp_reg = SCR_RES1_BITS | SCR_RW_BIT; 245 write_scr(tmp_reg); 246 247 INFO("BL3-1: Tegra platform setup complete\n"); 248 } 249 250 /******************************************************************************* 251 * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit 252 ******************************************************************************/ 253 void bl31_plat_runtime_setup(void) 254 { 255 /* Initialize the runtime console */ 256 console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ, 257 TEGRA_CONSOLE_BAUDRATE); 258 } 259 260 /******************************************************************************* 261 * Perform the very early platform specific architectural setup here. At the 262 * moment this only intializes the mmu in a quick and dirty way. 263 ******************************************************************************/ 264 void bl31_plat_arch_setup(void) 265 { 266 unsigned long bl31_base_pa = tegra_bl31_phys_base; 267 unsigned long total_base = bl31_base_pa; 268 unsigned long total_size = BL32_BASE - BL31_RO_BASE; 269 unsigned long ro_start = bl31_base_pa; 270 unsigned long ro_size = BL31_RO_LIMIT - BL31_RO_BASE; 271 const mmap_region_t *plat_mmio_map = NULL; 272 #if USE_COHERENT_MEM 273 unsigned long coh_start, coh_size; 274 #endif 275 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 276 277 /* add memory regions */ 278 mmap_add_region(total_base, total_base, 279 total_size, 280 MT_MEMORY | MT_RW | MT_SECURE); 281 mmap_add_region(ro_start, ro_start, 282 ro_size, 283 MT_MEMORY | MT_RO | MT_SECURE); 284 285 /* map TZDRAM used by BL31 as coherent memory */ 286 if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) { 287 mmap_add_region(params_from_bl2->tzdram_base, 288 params_from_bl2->tzdram_base, 289 BL31_SIZE, 290 MT_DEVICE | MT_RW | MT_SECURE); 291 } 292 293 #if USE_COHERENT_MEM 294 coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE); 295 coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE; 296 297 mmap_add_region(coh_start, coh_start, 298 coh_size, 299 MT_DEVICE | MT_RW | MT_SECURE); 300 #endif 301 302 /* add MMIO space */ 303 plat_mmio_map = plat_get_mmio_map(); 304 if (plat_mmio_map) 305 mmap_add(plat_mmio_map); 306 else 307 WARN("MMIO map not available\n"); 308 309 /* set up translation tables */ 310 init_xlat_tables(); 311 312 /* enable the MMU */ 313 enable_mmu_el3(0); 314 315 INFO("BL3-1: Tegra: MMU enabled\n"); 316 } 317 318 /******************************************************************************* 319 * Check if the given NS DRAM range is valid 320 ******************************************************************************/ 321 int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes) 322 { 323 uint64_t end = base + size_in_bytes - 1; 324 325 /* 326 * Check if the NS DRAM address is valid 327 */ 328 if ((base < TEGRA_DRAM_BASE) || (end > TEGRA_DRAM_END) || 329 (base >= end)) { 330 ERROR("NS address is out-of-bounds!\n"); 331 return -EFAULT; 332 } 333 334 /* 335 * TZDRAM aperture contains the BL31 and BL32 images, so we need 336 * to check if the NS DRAM range overlaps the TZDRAM aperture. 337 */ 338 if ((base < TZDRAM_END) && (end > tegra_bl31_phys_base)) { 339 ERROR("NS address overlaps TZDRAM!\n"); 340 return -ENOTSUP; 341 } 342 343 /* valid NS address */ 344 return 0; 345 } 346