1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <errno.h> 10 #include <stddef.h> 11 #include <string.h> 12 13 #include <platform_def.h> 14 15 #include <arch.h> 16 #include <arch_helpers.h> 17 #include <bl31/bl31.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <cortex_a53.h> 21 #include <cortex_a57.h> 22 #include <denver.h> 23 #include <drivers/console.h> 24 #include <lib/mmio.h> 25 #include <lib/utils.h> 26 #include <lib/utils_def.h> 27 #include <plat/common/platform.h> 28 29 #include <memctrl.h> 30 #include <profiler.h> 31 #include <tegra_def.h> 32 #include <tegra_platform.h> 33 #include <tegra_private.h> 34 35 /* length of Trusty's input parameters (in bytes) */ 36 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 37 38 /******************************************************************************* 39 * Declarations of linker defined symbols which will help us find the layout 40 * of trusted SRAM 41 ******************************************************************************/ 42 43 IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START); 44 45 static const uint64_t BL31_RW_END = BL_END; 46 static const uint64_t BL31_RODATA_BASE = BL_RO_DATA_BASE; 47 static const uint64_t BL31_RODATA_END = BL_RO_DATA_END; 48 static const uint64_t TEXT_START = BL_CODE_BASE; 49 static const uint64_t TEXT_END = BL_CODE_END; 50 51 extern uint64_t tegra_bl31_phys_base; 52 53 static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; 54 static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { 55 .tzdram_size = TZDRAM_SIZE 56 }; 57 #ifdef SPD_trusty 58 static aapcs64_params_t bl32_args; 59 #endif 60 61 /******************************************************************************* 62 * This variable holds the non-secure image entry address 63 ******************************************************************************/ 64 extern uint64_t ns_image_entrypoint; 65 66 /******************************************************************************* 67 * Return a pointer to the 'entry_point_info' structure of the next image for 68 * security state specified. BL33 corresponds to the non-secure image type 69 * while BL32 corresponds to the secure image type. 70 ******************************************************************************/ 71 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 72 { 73 entry_point_info_t *ep = NULL; 74 75 /* return BL32 entry point info if it is valid */ 76 if (type == NON_SECURE) { 77 ep = &bl33_image_ep_info; 78 } else if ((type == SECURE) && (bl32_image_ep_info.pc != 0U)) { 79 ep = &bl32_image_ep_info; 80 } 81 82 return ep; 83 } 84 85 /******************************************************************************* 86 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image 87 * passes this platform specific information. 88 ******************************************************************************/ 89 plat_params_from_bl2_t *bl31_get_plat_params(void) 90 { 91 return &plat_bl31_params_from_bl2; 92 } 93 94 /******************************************************************************* 95 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image 96 * info. 97 ******************************************************************************/ 98 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 99 u_register_t arg2, u_register_t arg3) 100 { 101 struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0; 102 plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1; 103 int32_t ret; 104 105 /* 106 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so 107 * there's no argument to relay from a previous bootloader. Platforms 108 * might use custom ways to get arguments. 109 */ 110 if (arg_from_bl2 == NULL) { 111 arg_from_bl2 = plat_get_bl31_params(); 112 } 113 if (plat_params == NULL) { 114 plat_params = plat_get_bl31_plat_params(); 115 } 116 117 /* 118 * Copy BL3-3, BL3-2 entry point information. 119 * They are stored in Secure RAM, in BL2's address space. 120 */ 121 assert(arg_from_bl2 != NULL); 122 assert(arg_from_bl2->bl33_ep_info != NULL); 123 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info; 124 125 if (arg_from_bl2->bl32_ep_info != NULL) { 126 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info; 127 #ifdef SPD_trusty 128 /* save BL32 boot parameters */ 129 memcpy(&bl32_args, &arg_from_bl2->bl32_ep_info->args, sizeof(bl32_args)); 130 #endif 131 } 132 133 /* 134 * Parse platform specific parameters 135 */ 136 assert(plat_params != NULL); 137 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base; 138 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; 139 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id; 140 plat_bl31_params_from_bl2.l2_ecc_parity_prot_dis = plat_params->l2_ecc_parity_prot_dis; 141 plat_bl31_params_from_bl2.sc7entry_fw_size = plat_params->sc7entry_fw_size; 142 plat_bl31_params_from_bl2.sc7entry_fw_base = plat_params->sc7entry_fw_base; 143 144 /* 145 * It is very important that we run either from TZDRAM or TZSRAM base. 146 * Add an explicit check here. 147 */ 148 if ((plat_bl31_params_from_bl2.tzdram_base != (uint64_t)BL31_BASE) && 149 (TEGRA_TZRAM_BASE != BL31_BASE)) { 150 panic(); 151 } 152 153 /* 154 * Enable console for the platform 155 */ 156 plat_enable_console(plat_params->uart_id); 157 158 /* 159 * The previous bootloader passes the base address of the shared memory 160 * location to store the boot profiler logs. Sanity check the 161 * address and initialise the profiler library, if it looks ok. 162 */ 163 ret = bl31_check_ns_address(plat_params->boot_profiler_shmem_base, 164 PROFILER_SIZE_BYTES); 165 if (ret == (int32_t)0) { 166 167 /* store the membase for the profiler lib */ 168 plat_bl31_params_from_bl2.boot_profiler_shmem_base = 169 plat_params->boot_profiler_shmem_base; 170 171 /* initialise the profiler library */ 172 boot_profiler_init(plat_params->boot_profiler_shmem_base, 173 TEGRA_TMRUS_BASE); 174 } 175 176 /* 177 * Add timestamp for platform early setup entry. 178 */ 179 boot_profiler_add_record("[TF] early setup entry"); 180 181 /* 182 * Initialize delay timer 183 */ 184 tegra_delay_timer_init(); 185 186 /* Early platform setup for Tegra SoCs */ 187 plat_early_platform_setup(); 188 189 /* 190 * Do initial security configuration to allow DRAM/device access. 191 */ 192 tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base, 193 (uint32_t)plat_bl31_params_from_bl2.tzdram_size); 194 195 #if RELOCATE_BL32_IMAGE 196 /* 197 * The previous bootloader might not have placed the BL32 image 198 * inside the TZDRAM. Platform handler to allow relocation of BL32 199 * image to TZDRAM memory. This behavior might change per platform. 200 */ 201 plat_relocate_bl32_image(arg_from_bl2->bl32_image_info); 202 #endif 203 204 /* 205 * Add timestamp for platform early setup exit. 206 */ 207 boot_profiler_add_record("[TF] early setup exit"); 208 209 INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", 210 (((read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK) 211 == DENVER_IMPL) ? "Denver" : "ARM", read_mpidr()); 212 } 213 214 #ifdef SPD_trusty 215 void plat_trusty_set_boot_args(aapcs64_params_t *args) 216 { 217 /* 218 * arg0 = TZDRAM aperture available for BL32 219 * arg1 = BL32 boot params 220 * arg2 = EKS Blob Length 221 * arg3 = Boot Profiler Carveout Base 222 */ 223 args->arg0 = bl32_args.arg0; 224 args->arg1 = bl32_args.arg2; 225 226 /* update EKS size */ 227 args->arg2 = bl32_args.arg4; 228 229 /* Profiler Carveout Base */ 230 args->arg3 = bl32_args.arg5; 231 } 232 #endif 233 234 /******************************************************************************* 235 * Initialize the gic, configure the SCR. 236 ******************************************************************************/ 237 void bl31_platform_setup(void) 238 { 239 /* 240 * Add timestamp for platform setup entry. 241 */ 242 boot_profiler_add_record("[TF] plat setup entry"); 243 244 /* Initialize the gic cpu and distributor interfaces */ 245 plat_gic_setup(); 246 247 /* 248 * Setup secondary CPU POR infrastructure. 249 */ 250 plat_secondary_setup(); 251 252 /* 253 * Initial Memory Controller configuration. 254 */ 255 tegra_memctrl_setup(); 256 257 /* 258 * Set up the TZRAM memory aperture to allow only secure world 259 * access 260 */ 261 tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE); 262 263 /* 264 * Late setup handler to allow platforms to performs additional 265 * functionality. 266 * This handler gets called with MMU enabled. 267 */ 268 plat_late_platform_setup(); 269 270 /* 271 * Add timestamp for platform setup exit. 272 */ 273 boot_profiler_add_record("[TF] plat setup exit"); 274 275 INFO("BL3-1: Tegra platform setup complete\n"); 276 } 277 278 /******************************************************************************* 279 * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit 280 ******************************************************************************/ 281 void bl31_plat_runtime_setup(void) 282 { 283 /* 284 * During cold boot, it is observed that the arbitration 285 * bit is set in the Memory controller leading to false 286 * error interrupts in the non-secure world. To avoid 287 * this, clean the interrupt status register before 288 * booting into the non-secure world 289 */ 290 tegra_memctrl_clear_pending_interrupts(); 291 292 /* 293 * During boot, USB3 and flash media (SDMMC/SATA) devices need 294 * access to IRAM. Because these clients connect to the MC and 295 * do not have a direct path to the IRAM, the MC implements AHB 296 * redirection during boot to allow path to IRAM. In this mode 297 * accesses to a programmed memory address aperture are directed 298 * to the AHB bus, allowing access to the IRAM. This mode must be 299 * disabled before we jump to the non-secure world. 300 */ 301 tegra_memctrl_disable_ahb_redirection(); 302 303 /* 304 * Add final timestamp before exiting BL31. 305 */ 306 boot_profiler_add_record("[TF] bl31 exit"); 307 boot_profiler_deinit(); 308 } 309 310 /******************************************************************************* 311 * Perform the very early platform specific architectural setup here. At the 312 * moment this only intializes the mmu in a quick and dirty way. 313 ******************************************************************************/ 314 void bl31_plat_arch_setup(void) 315 { 316 uint64_t rw_start = BL31_RW_START; 317 uint64_t rw_size = BL31_RW_END - BL31_RW_START; 318 uint64_t rodata_start = BL31_RODATA_BASE; 319 uint64_t rodata_size = BL31_RODATA_END - BL31_RODATA_BASE; 320 uint64_t code_base = TEXT_START; 321 uint64_t code_size = TEXT_END - TEXT_START; 322 const mmap_region_t *plat_mmio_map = NULL; 323 #if USE_COHERENT_MEM 324 uint32_t coh_start, coh_size; 325 #endif 326 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 327 328 /* 329 * Add timestamp for arch setup entry. 330 */ 331 boot_profiler_add_record("[TF] arch setup entry"); 332 333 /* add MMIO space */ 334 plat_mmio_map = plat_get_mmio_map(); 335 if (plat_mmio_map != NULL) { 336 mmap_add(plat_mmio_map); 337 } else { 338 WARN("MMIO map not available\n"); 339 } 340 341 /* add memory regions */ 342 mmap_add_region(rw_start, rw_start, 343 rw_size, 344 MT_MEMORY | MT_RW | MT_SECURE); 345 mmap_add_region(rodata_start, rodata_start, 346 rodata_size, 347 MT_RO_DATA | MT_SECURE); 348 mmap_add_region(code_base, code_base, 349 code_size, 350 MT_CODE | MT_SECURE); 351 352 #if USE_COHERENT_MEM 353 coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE); 354 coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE; 355 356 mmap_add_region(coh_start, coh_start, 357 coh_size, 358 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE); 359 #endif 360 361 /* map TZDRAM used by BL31 as coherent memory */ 362 if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) { 363 mmap_add_region(params_from_bl2->tzdram_base, 364 params_from_bl2->tzdram_base, 365 BL31_SIZE, 366 MT_DEVICE | MT_RW | MT_SECURE); 367 } 368 369 /* set up translation tables */ 370 init_xlat_tables(); 371 372 /* enable the MMU */ 373 enable_mmu_el3(0); 374 375 /* 376 * Add timestamp for arch setup exit. 377 */ 378 boot_profiler_add_record("[TF] arch setup exit"); 379 380 INFO("BL3-1: Tegra: MMU enabled\n"); 381 } 382 383 /******************************************************************************* 384 * Check if the given NS DRAM range is valid 385 ******************************************************************************/ 386 int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes) 387 { 388 uint64_t end = base + size_in_bytes - U(1); 389 int32_t ret = 0; 390 391 /* 392 * Check if the NS DRAM address is valid 393 */ 394 if ((base < TEGRA_DRAM_BASE) || (base >= TEGRA_DRAM_END) || 395 (end > TEGRA_DRAM_END)) { 396 397 ERROR("NS address 0x%llx is out-of-bounds!\n", base); 398 ret = -EFAULT; 399 } 400 401 /* 402 * TZDRAM aperture contains the BL31 and BL32 images, so we need 403 * to check if the NS DRAM range overlaps the TZDRAM aperture. 404 */ 405 if ((base < (uint64_t)TZDRAM_END) && (end > tegra_bl31_phys_base)) { 406 ERROR("NS address 0x%llx overlaps TZDRAM!\n", base); 407 ret = -ENOTSUP; 408 } 409 410 /* valid NS address */ 411 return ret; 412 } 413