1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <stddef.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <bl31/bl31.h> 17 #include <common/bl_common.h> 18 #include <common/debug.h> 19 #include <cortex_a53.h> 20 #include <cortex_a57.h> 21 #include <denver.h> 22 #include <drivers/console.h> 23 #include <lib/mmio.h> 24 #include <lib/utils.h> 25 #include <lib/utils_def.h> 26 #include <plat/common/platform.h> 27 28 #include <memctrl.h> 29 #include <tegra_def.h> 30 #include <tegra_platform.h> 31 #include <tegra_private.h> 32 33 /* length of Trusty's input parameters (in bytes) */ 34 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 35 36 extern void memcpy16(void *dest, const void *src, unsigned int length); 37 38 /******************************************************************************* 39 * Declarations of linker defined symbols which will help us find the layout 40 * of trusted SRAM 41 ******************************************************************************/ 42 43 IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START); 44 IMPORT_SYM(uint64_t, __RW_END__, BL31_RW_END); 45 IMPORT_SYM(uint64_t, __RODATA_START__, BL31_RODATA_BASE); 46 IMPORT_SYM(uint64_t, __RODATA_END__, BL31_RODATA_END); 47 IMPORT_SYM(uint64_t, __TEXT_START__, TEXT_START); 48 IMPORT_SYM(uint64_t, __TEXT_END__, TEXT_END); 49 50 extern uint64_t tegra_bl31_phys_base; 51 extern uint64_t tegra_console_base; 52 53 static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; 54 static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { 55 .tzdram_size = TZDRAM_SIZE 56 }; 57 static unsigned long bl32_mem_size; 58 static unsigned long bl32_boot_params; 59 60 /******************************************************************************* 61 * This variable holds the non-secure image entry address 62 ******************************************************************************/ 63 extern uint64_t ns_image_entrypoint; 64 65 /******************************************************************************* 66 * The following platform setup functions are weakly defined. They 67 * provide typical implementations that will be overridden by a SoC. 68 ******************************************************************************/ 69 #pragma weak plat_early_platform_setup 70 #pragma weak plat_get_bl31_params 71 #pragma weak plat_get_bl31_plat_params 72 73 void plat_early_platform_setup(void) 74 { 75 ; /* do nothing */ 76 } 77 78 struct tegra_bl31_params *plat_get_bl31_params(void) 79 { 80 return NULL; 81 } 82 83 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 84 { 85 return NULL; 86 } 87 88 /******************************************************************************* 89 * Return a pointer to the 'entry_point_info' structure of the next image for 90 * security state specified. BL33 corresponds to the non-secure image type 91 * while BL32 corresponds to the secure image type. 92 ******************************************************************************/ 93 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 94 { 95 entry_point_info_t *ep = NULL; 96 97 /* return BL32 entry point info if it is valid */ 98 if (type == NON_SECURE) { 99 ep = &bl33_image_ep_info; 100 } else if ((type == SECURE) && (bl32_image_ep_info.pc != 0U)) { 101 ep = &bl32_image_ep_info; 102 } 103 104 return ep; 105 } 106 107 /******************************************************************************* 108 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image 109 * passes this platform specific information. 110 ******************************************************************************/ 111 plat_params_from_bl2_t *bl31_get_plat_params(void) 112 { 113 return &plat_bl31_params_from_bl2; 114 } 115 116 /******************************************************************************* 117 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image 118 * info. 119 ******************************************************************************/ 120 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 121 u_register_t arg2, u_register_t arg3) 122 { 123 struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0; 124 plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1; 125 image_info_t bl32_img_info = { {0} }; 126 uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end; 127 uint32_t console_clock; 128 129 /* 130 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so 131 * there's no argument to relay from a previous bootloader. Platforms 132 * might use custom ways to get arguments, so provide handlers which 133 * they can override. 134 */ 135 if (arg_from_bl2 == NULL) { 136 arg_from_bl2 = plat_get_bl31_params(); 137 } 138 if (plat_params == NULL) { 139 plat_params = plat_get_bl31_plat_params(); 140 } 141 142 /* 143 * Copy BL3-3, BL3-2 entry point information. 144 * They are stored in Secure RAM, in BL2's address space. 145 */ 146 assert(arg_from_bl2 != NULL); 147 assert(arg_from_bl2->bl33_ep_info != NULL); 148 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info; 149 150 if (arg_from_bl2->bl32_ep_info != NULL) { 151 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info; 152 bl32_mem_size = arg_from_bl2->bl32_ep_info->args.arg0; 153 bl32_boot_params = arg_from_bl2->bl32_ep_info->args.arg2; 154 } 155 156 /* 157 * Parse platform specific parameters - TZDRAM aperture base and size 158 */ 159 assert(plat_params != NULL); 160 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base; 161 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; 162 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id; 163 plat_bl31_params_from_bl2.l2_ecc_parity_prot_dis = plat_params->l2_ecc_parity_prot_dis; 164 165 /* 166 * It is very important that we run either from TZDRAM or TZSRAM base. 167 * Add an explicit check here. 168 */ 169 if ((plat_bl31_params_from_bl2.tzdram_base != (uint64_t)BL31_BASE) && 170 (TEGRA_TZRAM_BASE != BL31_BASE)) { 171 panic(); 172 } 173 174 /* 175 * Reference clock used by the FPGAs is a lot slower. 176 */ 177 if (tegra_platform_is_fpga()) { 178 console_clock = TEGRA_BOOT_UART_CLK_13_MHZ; 179 } else { 180 console_clock = TEGRA_BOOT_UART_CLK_408_MHZ; 181 } 182 183 /* 184 * Get the base address of the UART controller to be used for the 185 * console 186 */ 187 tegra_console_base = plat_get_console_from_id(plat_params->uart_id); 188 189 if (tegra_console_base != 0U) { 190 /* 191 * Configure the UART port to be used as the console 192 */ 193 (void)console_init(tegra_console_base, console_clock, 194 TEGRA_CONSOLE_BAUDRATE); 195 } 196 197 /* 198 * Initialize delay timer 199 */ 200 tegra_delay_timer_init(); 201 202 /* 203 * Do initial security configuration to allow DRAM/device access. 204 */ 205 tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base, 206 (uint32_t)plat_bl31_params_from_bl2.tzdram_size); 207 208 /* 209 * The previous bootloader might not have placed the BL32 image 210 * inside the TZDRAM. We check the BL32 image info to find out 211 * the base/PC values and relocate the image if necessary. 212 */ 213 if (arg_from_bl2->bl32_image_info != NULL) { 214 215 bl32_img_info = *arg_from_bl2->bl32_image_info; 216 217 /* Relocate BL32 if it resides outside of the TZDRAM */ 218 tzdram_start = plat_bl31_params_from_bl2.tzdram_base; 219 tzdram_end = plat_bl31_params_from_bl2.tzdram_base + 220 plat_bl31_params_from_bl2.tzdram_size; 221 bl32_start = bl32_img_info.image_base; 222 bl32_end = bl32_img_info.image_base + bl32_img_info.image_size; 223 224 assert(tzdram_end > tzdram_start); 225 assert(bl32_end > bl32_start); 226 assert(bl32_image_ep_info.pc > tzdram_start); 227 assert(bl32_image_ep_info.pc < tzdram_end); 228 229 /* relocate BL32 */ 230 if ((bl32_start >= tzdram_end) || (bl32_end <= tzdram_start)) { 231 232 INFO("Relocate BL32 to TZDRAM\n"); 233 234 (void)memcpy16((void *)(uintptr_t)bl32_image_ep_info.pc, 235 (void *)(uintptr_t)bl32_start, 236 bl32_img_info.image_size); 237 238 /* clean up non-secure intermediate buffer */ 239 zeromem((void *)(uintptr_t)bl32_start, 240 bl32_img_info.image_size); 241 } 242 } 243 244 /* Early platform setup for Tegra SoCs */ 245 plat_early_platform_setup(); 246 247 INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", 248 (((read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK) 249 == DENVER_IMPL) ? "Denver" : "ARM", read_mpidr()); 250 } 251 252 #ifdef SPD_trusty 253 void plat_trusty_set_boot_args(aapcs64_params_t *args) 254 { 255 args->arg0 = bl32_mem_size; 256 args->arg1 = bl32_boot_params; 257 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 258 259 /* update EKS size */ 260 if (args->arg4 != 0U) { 261 args->arg2 = args->arg4; 262 } 263 } 264 #endif 265 266 /******************************************************************************* 267 * Initialize the gic, configure the SCR. 268 ******************************************************************************/ 269 void bl31_platform_setup(void) 270 { 271 /* Initialize the gic cpu and distributor interfaces */ 272 plat_gic_setup(); 273 274 /* 275 * Setup secondary CPU POR infrastructure. 276 */ 277 plat_secondary_setup(); 278 279 /* 280 * Initial Memory Controller configuration. 281 */ 282 tegra_memctrl_setup(); 283 284 /* 285 * Set up the TZRAM memory aperture to allow only secure world 286 * access 287 */ 288 tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE); 289 290 INFO("BL3-1: Tegra platform setup complete\n"); 291 } 292 293 /******************************************************************************* 294 * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit 295 ******************************************************************************/ 296 void bl31_plat_runtime_setup(void) 297 { 298 /* 299 * During boot, USB3 and flash media (SDMMC/SATA) devices need 300 * access to IRAM. Because these clients connect to the MC and 301 * do not have a direct path to the IRAM, the MC implements AHB 302 * redirection during boot to allow path to IRAM. In this mode 303 * accesses to a programmed memory address aperture are directed 304 * to the AHB bus, allowing access to the IRAM. This mode must be 305 * disabled before we jump to the non-secure world. 306 */ 307 tegra_memctrl_disable_ahb_redirection(); 308 } 309 310 /******************************************************************************* 311 * Perform the very early platform specific architectural setup here. At the 312 * moment this only intializes the mmu in a quick and dirty way. 313 ******************************************************************************/ 314 void bl31_plat_arch_setup(void) 315 { 316 uint64_t rw_start = BL31_RW_START; 317 uint64_t rw_size = BL31_RW_END - BL31_RW_START; 318 uint64_t rodata_start = BL31_RODATA_BASE; 319 uint64_t rodata_size = BL31_RODATA_END - BL31_RODATA_BASE; 320 uint64_t code_base = TEXT_START; 321 uint64_t code_size = TEXT_END - TEXT_START; 322 const mmap_region_t *plat_mmio_map = NULL; 323 #if USE_COHERENT_MEM 324 uint32_t coh_start, coh_size; 325 #endif 326 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 327 328 /* add memory regions */ 329 mmap_add_region(rw_start, rw_start, 330 rw_size, 331 MT_MEMORY | MT_RW | MT_SECURE); 332 mmap_add_region(rodata_start, rodata_start, 333 rodata_size, 334 MT_RO_DATA | MT_SECURE); 335 mmap_add_region(code_base, code_base, 336 code_size, 337 MT_CODE | MT_SECURE); 338 339 /* map TZDRAM used by BL31 as coherent memory */ 340 if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) { 341 mmap_add_region(params_from_bl2->tzdram_base, 342 params_from_bl2->tzdram_base, 343 BL31_SIZE, 344 MT_DEVICE | MT_RW | MT_SECURE); 345 } 346 347 #if USE_COHERENT_MEM 348 coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE); 349 coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE; 350 351 mmap_add_region(coh_start, coh_start, 352 coh_size, 353 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE); 354 #endif 355 356 /* map on-chip free running uS timer */ 357 mmap_add_region(page_align(TEGRA_TMRUS_BASE, 0), 358 page_align(TEGRA_TMRUS_BASE, 0), 359 TEGRA_TMRUS_SIZE, 360 (uint8_t)MT_DEVICE | (uint8_t)MT_RO | (uint8_t)MT_SECURE); 361 362 /* add MMIO space */ 363 plat_mmio_map = plat_get_mmio_map(); 364 if (plat_mmio_map != NULL) { 365 mmap_add(plat_mmio_map); 366 } else { 367 WARN("MMIO map not available\n"); 368 } 369 370 /* set up translation tables */ 371 init_xlat_tables(); 372 373 /* enable the MMU */ 374 enable_mmu_el3(0); 375 376 INFO("BL3-1: Tegra: MMU enabled\n"); 377 } 378 379 /******************************************************************************* 380 * Check if the given NS DRAM range is valid 381 ******************************************************************************/ 382 int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes) 383 { 384 uint64_t end = base + size_in_bytes - U(1); 385 int32_t ret = 0; 386 387 /* 388 * Check if the NS DRAM address is valid 389 */ 390 if ((base < TEGRA_DRAM_BASE) || (base >= TEGRA_DRAM_END) || 391 (end > TEGRA_DRAM_END)) { 392 393 ERROR("NS address is out-of-bounds!\n"); 394 ret = -EFAULT; 395 } 396 397 /* 398 * TZDRAM aperture contains the BL31 and BL32 images, so we need 399 * to check if the NS DRAM range overlaps the TZDRAM aperture. 400 */ 401 if ((base < (uint64_t)TZDRAM_END) && (end > tegra_bl31_phys_base)) { 402 ERROR("NS address overlaps TZDRAM!\n"); 403 ret = -ENOTSUP; 404 } 405 406 /* valid NS address */ 407 return ret; 408 } 409