1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <bl31.h> 11 #include <bl_common.h> 12 #include <console.h> 13 #include <cortex_a53.h> 14 #include <cortex_a57.h> 15 #include <debug.h> 16 #include <denver.h> 17 #include <errno.h> 18 #include <memctrl.h> 19 #include <mmio.h> 20 #include <platform.h> 21 #include <platform_def.h> 22 #include <stddef.h> 23 #include <string.h> 24 #include <tegra_def.h> 25 #include <tegra_private.h> 26 #include <utils_def.h> 27 28 /* length of Trusty's input parameters (in bytes) */ 29 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 30 31 extern void zeromem16(void *mem, unsigned int length); 32 33 /******************************************************************************* 34 * Declarations of linker defined symbols which will help us find the layout 35 * of trusted SRAM 36 ******************************************************************************/ 37 38 IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START); 39 IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END); 40 IMPORT_SYM(unsigned long, __RODATA_START__, BL31_RODATA_BASE); 41 IMPORT_SYM(unsigned long, __RODATA_END__, BL31_RODATA_END); 42 IMPORT_SYM(unsigned long, __TEXT_START__, TEXT_START); 43 IMPORT_SYM(unsigned long, __TEXT_END__, TEXT_END); 44 45 extern uint64_t tegra_bl31_phys_base; 46 extern uint64_t tegra_console_base; 47 48 49 static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; 50 static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { 51 .tzdram_size = (uint64_t)TZDRAM_SIZE 52 }; 53 static unsigned long bl32_mem_size; 54 static unsigned long bl32_boot_params; 55 56 /******************************************************************************* 57 * This variable holds the non-secure image entry address 58 ******************************************************************************/ 59 extern uint64_t ns_image_entrypoint; 60 61 /******************************************************************************* 62 * The following platform setup functions are weakly defined. They 63 * provide typical implementations that will be overridden by a SoC. 64 ******************************************************************************/ 65 #pragma weak plat_early_platform_setup 66 #pragma weak plat_get_bl31_params 67 #pragma weak plat_get_bl31_plat_params 68 69 void plat_early_platform_setup(void) 70 { 71 ; /* do nothing */ 72 } 73 74 bl31_params_t *plat_get_bl31_params(void) 75 { 76 return NULL; 77 } 78 79 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 80 { 81 return NULL; 82 } 83 84 /******************************************************************************* 85 * Return a pointer to the 'entry_point_info' structure of the next image for 86 * security state specified. BL33 corresponds to the non-secure image type 87 * while BL32 corresponds to the secure image type. 88 ******************************************************************************/ 89 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 90 { 91 if (type == NON_SECURE) 92 return &bl33_image_ep_info; 93 94 /* return BL32 entry point info if it is valid */ 95 if (type == SECURE && bl32_image_ep_info.pc) 96 return &bl32_image_ep_info; 97 98 return NULL; 99 } 100 101 /******************************************************************************* 102 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image 103 * passes this platform specific information. 104 ******************************************************************************/ 105 plat_params_from_bl2_t *bl31_get_plat_params(void) 106 { 107 return &plat_bl31_params_from_bl2; 108 } 109 110 /******************************************************************************* 111 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image 112 * info. 113 ******************************************************************************/ 114 void bl31_early_platform_setup(bl31_params_t *from_bl2, 115 void *plat_params_from_bl2) 116 { 117 plat_params_from_bl2_t *plat_params = 118 (plat_params_from_bl2_t *)plat_params_from_bl2; 119 image_info_t bl32_img_info = { {0} }; 120 uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end; 121 122 /* 123 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so 124 * there's no argument to relay from a previous bootloader. Platforms 125 * might use custom ways to get arguments, so provide handlers which 126 * they can override. 127 */ 128 if (from_bl2 == NULL) 129 from_bl2 = plat_get_bl31_params(); 130 if (plat_params == NULL) 131 plat_params = plat_get_bl31_plat_params(); 132 133 /* 134 * Copy BL3-3, BL3-2 entry point information. 135 * They are stored in Secure RAM, in BL2's address space. 136 */ 137 assert(from_bl2); 138 assert(from_bl2->bl33_ep_info); 139 bl33_image_ep_info = *from_bl2->bl33_ep_info; 140 141 if (from_bl2->bl32_ep_info) { 142 bl32_image_ep_info = *from_bl2->bl32_ep_info; 143 bl32_mem_size = from_bl2->bl32_ep_info->args.arg0; 144 bl32_boot_params = from_bl2->bl32_ep_info->args.arg2; 145 } 146 147 /* 148 * Parse platform specific parameters - TZDRAM aperture base and size 149 */ 150 assert(plat_params); 151 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base; 152 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; 153 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id; 154 155 /* 156 * It is very important that we run either from TZDRAM or TZSRAM base. 157 * Add an explicit check here. 158 */ 159 if ((plat_bl31_params_from_bl2.tzdram_base != BL31_BASE) && 160 (TEGRA_TZRAM_BASE != BL31_BASE)) 161 panic(); 162 163 /* 164 * Get the base address of the UART controller to be used for the 165 * console 166 */ 167 tegra_console_base = plat_get_console_from_id(plat_params->uart_id); 168 169 if (tegra_console_base != (uint64_t)0) { 170 /* 171 * Configure the UART port to be used as the console 172 */ 173 console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ, 174 TEGRA_CONSOLE_BAUDRATE); 175 } 176 177 /* 178 * Initialize delay timer 179 */ 180 tegra_delay_timer_init(); 181 182 /* 183 * Do initial security configuration to allow DRAM/device access. 184 */ 185 tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base, 186 plat_bl31_params_from_bl2.tzdram_size); 187 188 /* 189 * The previous bootloader might not have placed the BL32 image 190 * inside the TZDRAM. We check the BL32 image info to find out 191 * the base/PC values and relocate the image if necessary. 192 */ 193 if (from_bl2->bl32_image_info) { 194 195 bl32_img_info = *from_bl2->bl32_image_info; 196 197 /* Relocate BL32 if it resides outside of the TZDRAM */ 198 tzdram_start = plat_bl31_params_from_bl2.tzdram_base; 199 tzdram_end = plat_bl31_params_from_bl2.tzdram_base + 200 plat_bl31_params_from_bl2.tzdram_size; 201 bl32_start = bl32_img_info.image_base; 202 bl32_end = bl32_img_info.image_base + bl32_img_info.image_size; 203 204 assert(tzdram_end > tzdram_start); 205 assert(bl32_end > bl32_start); 206 assert(bl32_image_ep_info.pc > tzdram_start); 207 assert(bl32_image_ep_info.pc < tzdram_end); 208 209 /* relocate BL32 */ 210 if (bl32_start >= tzdram_end || bl32_end <= tzdram_start) { 211 212 INFO("Relocate BL32 to TZDRAM\n"); 213 214 memcpy16((void *)(uintptr_t)bl32_image_ep_info.pc, 215 (void *)(uintptr_t)bl32_start, 216 bl32_img_info.image_size); 217 218 /* clean up non-secure intermediate buffer */ 219 zeromem16((void *)(uintptr_t)bl32_start, 220 bl32_img_info.image_size); 221 } 222 } 223 224 /* Early platform setup for Tegra SoCs */ 225 plat_early_platform_setup(); 226 227 INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", 228 (((read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK) 229 == DENVER_IMPL) ? "Denver" : "ARM", read_mpidr()); 230 } 231 232 #ifdef SPD_trusty 233 void plat_trusty_set_boot_args(aapcs64_params_t *args) 234 { 235 args->arg0 = bl32_mem_size; 236 args->arg1 = bl32_boot_params; 237 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 238 } 239 #endif 240 241 /******************************************************************************* 242 * Initialize the gic, configure the SCR. 243 ******************************************************************************/ 244 void bl31_platform_setup(void) 245 { 246 uint32_t tmp_reg; 247 248 /* Initialize the gic cpu and distributor interfaces */ 249 plat_gic_setup(); 250 251 /* 252 * Setup secondary CPU POR infrastructure. 253 */ 254 plat_secondary_setup(); 255 256 /* 257 * Initial Memory Controller configuration. 258 */ 259 tegra_memctrl_setup(); 260 261 /* 262 * Set up the TZRAM memory aperture to allow only secure world 263 * access 264 */ 265 tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE); 266 267 /* Set the next EL to be AArch64 */ 268 tmp_reg = SCR_RES1_BITS | SCR_RW_BIT; 269 write_scr(tmp_reg); 270 271 INFO("BL3-1: Tegra platform setup complete\n"); 272 } 273 274 /******************************************************************************* 275 * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit 276 ******************************************************************************/ 277 void bl31_plat_runtime_setup(void) 278 { 279 /* 280 * During boot, USB3 and flash media (SDMMC/SATA) devices need 281 * access to IRAM. Because these clients connect to the MC and 282 * do not have a direct path to the IRAM, the MC implements AHB 283 * redirection during boot to allow path to IRAM. In this mode 284 * accesses to a programmed memory address aperture are directed 285 * to the AHB bus, allowing access to the IRAM. This mode must be 286 * disabled before we jump to the non-secure world. 287 */ 288 tegra_memctrl_disable_ahb_redirection(); 289 } 290 291 /******************************************************************************* 292 * Perform the very early platform specific architectural setup here. At the 293 * moment this only intializes the mmu in a quick and dirty way. 294 ******************************************************************************/ 295 void bl31_plat_arch_setup(void) 296 { 297 unsigned long rw_start = BL31_RW_START; 298 unsigned long rw_size = BL31_RW_END - BL31_RW_START; 299 unsigned long rodata_start = BL31_RODATA_BASE; 300 unsigned long rodata_size = BL31_RODATA_END - BL31_RODATA_BASE; 301 unsigned long code_base = TEXT_START; 302 unsigned long code_size = TEXT_END - TEXT_START; 303 const mmap_region_t *plat_mmio_map = NULL; 304 #if USE_COHERENT_MEM 305 unsigned long coh_start, coh_size; 306 #endif 307 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 308 309 /* add memory regions */ 310 mmap_add_region(rw_start, rw_start, 311 rw_size, 312 MT_MEMORY | MT_RW | MT_SECURE); 313 mmap_add_region(rodata_start, rodata_start, 314 rodata_size, 315 MT_RO_DATA | MT_SECURE); 316 mmap_add_region(code_base, code_base, 317 code_size, 318 MT_CODE | MT_SECURE); 319 320 /* map TZDRAM used by BL31 as coherent memory */ 321 if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) { 322 mmap_add_region(params_from_bl2->tzdram_base, 323 params_from_bl2->tzdram_base, 324 BL31_SIZE, 325 MT_DEVICE | MT_RW | MT_SECURE); 326 } 327 328 #if USE_COHERENT_MEM 329 coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE); 330 coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE; 331 332 mmap_add_region(coh_start, coh_start, 333 coh_size, 334 MT_DEVICE | MT_RW | MT_SECURE); 335 #endif 336 337 /* map on-chip free running uS timer */ 338 mmap_add_region(page_align((uint64_t)TEGRA_TMRUS_BASE, 0), 339 page_align((uint64_t)TEGRA_TMRUS_BASE, 0), 340 (uint64_t)TEGRA_TMRUS_SIZE, 341 MT_DEVICE | MT_RO | MT_SECURE); 342 343 /* add MMIO space */ 344 plat_mmio_map = plat_get_mmio_map(); 345 if (plat_mmio_map) 346 mmap_add(plat_mmio_map); 347 else 348 WARN("MMIO map not available\n"); 349 350 /* set up translation tables */ 351 init_xlat_tables(); 352 353 /* enable the MMU */ 354 enable_mmu_el3(0); 355 356 INFO("BL3-1: Tegra: MMU enabled\n"); 357 } 358 359 /******************************************************************************* 360 * Check if the given NS DRAM range is valid 361 ******************************************************************************/ 362 int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes) 363 { 364 uint64_t end = base + size_in_bytes; 365 366 /* 367 * Check if the NS DRAM address is valid 368 */ 369 if ((base < TEGRA_DRAM_BASE) || (end > TEGRA_DRAM_END)) { 370 ERROR("NS address is out-of-bounds!\n"); 371 return -EFAULT; 372 } 373 374 /* 375 * TZDRAM aperture contains the BL31 and BL32 images, so we need 376 * to check if the NS DRAM range overlaps the TZDRAM aperture. 377 */ 378 if ((base < TZDRAM_END) && (end > tegra_bl31_phys_base)) { 379 ERROR("NS address overlaps TZDRAM!\n"); 380 return -ENOTSUP; 381 } 382 383 /* valid NS address */ 384 return 0; 385 } 386