1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <stddef.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <bl31/bl31.h> 17 #include <common/bl_common.h> 18 #include <common/debug.h> 19 #include <cortex_a53.h> 20 #include <cortex_a57.h> 21 #include <denver.h> 22 #include <drivers/console.h> 23 #include <lib/mmio.h> 24 #include <lib/utils.h> 25 #include <lib/utils_def.h> 26 #include <plat/common/platform.h> 27 28 #include <memctrl.h> 29 #include <profiler.h> 30 #include <tegra_def.h> 31 #include <tegra_platform.h> 32 #include <tegra_private.h> 33 34 /* length of Trusty's input parameters (in bytes) */ 35 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 36 37 extern void memcpy16(void *dest, const void *src, unsigned int length); 38 39 /******************************************************************************* 40 * Declarations of linker defined symbols which will help us find the layout 41 * of trusted SRAM 42 ******************************************************************************/ 43 44 IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START); 45 46 static const uint64_t BL31_RW_END = BL_END; 47 static const uint64_t BL31_RODATA_BASE = BL_RO_DATA_BASE; 48 static const uint64_t BL31_RODATA_END = BL_RO_DATA_END; 49 static const uint64_t TEXT_START = BL_CODE_BASE; 50 static const uint64_t TEXT_END = BL_CODE_END; 51 52 extern uint64_t tegra_bl31_phys_base; 53 54 static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; 55 static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { 56 .tzdram_size = TZDRAM_SIZE 57 }; 58 #ifdef SPD_trusty 59 static aapcs64_params_t bl32_args; 60 #endif 61 62 /******************************************************************************* 63 * This variable holds the non-secure image entry address 64 ******************************************************************************/ 65 extern uint64_t ns_image_entrypoint; 66 67 /******************************************************************************* 68 * Return a pointer to the 'entry_point_info' structure of the next image for 69 * security state specified. BL33 corresponds to the non-secure image type 70 * while BL32 corresponds to the secure image type. 71 ******************************************************************************/ 72 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 73 { 74 entry_point_info_t *ep = NULL; 75 76 /* return BL32 entry point info if it is valid */ 77 if (type == NON_SECURE) { 78 ep = &bl33_image_ep_info; 79 } else if ((type == SECURE) && (bl32_image_ep_info.pc != 0U)) { 80 ep = &bl32_image_ep_info; 81 } 82 83 return ep; 84 } 85 86 /******************************************************************************* 87 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image 88 * passes this platform specific information. 89 ******************************************************************************/ 90 plat_params_from_bl2_t *bl31_get_plat_params(void) 91 { 92 return &plat_bl31_params_from_bl2; 93 } 94 95 /******************************************************************************* 96 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image 97 * info. 98 ******************************************************************************/ 99 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 100 u_register_t arg2, u_register_t arg3) 101 { 102 struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0; 103 plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1; 104 image_info_t bl32_img_info = { {0} }; 105 uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end; 106 int32_t ret; 107 108 /* 109 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so 110 * there's no argument to relay from a previous bootloader. Platforms 111 * might use custom ways to get arguments. 112 */ 113 if (arg_from_bl2 == NULL) { 114 arg_from_bl2 = plat_get_bl31_params(); 115 } 116 if (plat_params == NULL) { 117 plat_params = plat_get_bl31_plat_params(); 118 } 119 120 /* 121 * Copy BL3-3, BL3-2 entry point information. 122 * They are stored in Secure RAM, in BL2's address space. 123 */ 124 assert(arg_from_bl2 != NULL); 125 assert(arg_from_bl2->bl33_ep_info != NULL); 126 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info; 127 128 if (arg_from_bl2->bl32_ep_info != NULL) { 129 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info; 130 #ifdef SPD_trusty 131 /* save BL32 boot parameters */ 132 memcpy(&bl32_args, &arg_from_bl2->bl32_ep_info->args, sizeof(bl32_args)); 133 #endif 134 } 135 136 /* 137 * Parse platform specific parameters 138 */ 139 assert(plat_params != NULL); 140 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base; 141 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; 142 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id; 143 plat_bl31_params_from_bl2.l2_ecc_parity_prot_dis = plat_params->l2_ecc_parity_prot_dis; 144 plat_bl31_params_from_bl2.sc7entry_fw_size = plat_params->sc7entry_fw_size; 145 plat_bl31_params_from_bl2.sc7entry_fw_base = plat_params->sc7entry_fw_base; 146 147 /* 148 * It is very important that we run either from TZDRAM or TZSRAM base. 149 * Add an explicit check here. 150 */ 151 if ((plat_bl31_params_from_bl2.tzdram_base != (uint64_t)BL31_BASE) && 152 (TEGRA_TZRAM_BASE != BL31_BASE)) { 153 panic(); 154 } 155 156 /* 157 * Enable console for the platform 158 */ 159 plat_enable_console(plat_params->uart_id); 160 161 /* 162 * The previous bootloader passes the base address of the shared memory 163 * location to store the boot profiler logs. Sanity check the 164 * address and initialise the profiler library, if it looks ok. 165 */ 166 if (plat_params->boot_profiler_shmem_base != 0ULL) { 167 168 ret = bl31_check_ns_address(plat_params->boot_profiler_shmem_base, 169 PROFILER_SIZE_BYTES); 170 if (ret == (int32_t)0) { 171 172 /* store the membase for the profiler lib */ 173 plat_bl31_params_from_bl2.boot_profiler_shmem_base = 174 plat_params->boot_profiler_shmem_base; 175 176 /* initialise the profiler library */ 177 boot_profiler_init(plat_params->boot_profiler_shmem_base, 178 TEGRA_TMRUS_BASE); 179 } 180 } 181 182 /* 183 * Add timestamp for platform early setup entry. 184 */ 185 boot_profiler_add_record("[TF] early setup entry"); 186 187 /* 188 * Initialize delay timer 189 */ 190 tegra_delay_timer_init(); 191 192 /* Early platform setup for Tegra SoCs */ 193 plat_early_platform_setup(); 194 195 /* 196 * Do initial security configuration to allow DRAM/device access. 197 */ 198 tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base, 199 (uint32_t)plat_bl31_params_from_bl2.tzdram_size); 200 201 /* 202 * The previous bootloader might not have placed the BL32 image 203 * inside the TZDRAM. We check the BL32 image info to find out 204 * the base/PC values and relocate the image if necessary. 205 */ 206 if (arg_from_bl2->bl32_image_info != NULL) { 207 208 bl32_img_info = *arg_from_bl2->bl32_image_info; 209 210 /* Relocate BL32 if it resides outside of the TZDRAM */ 211 tzdram_start = plat_bl31_params_from_bl2.tzdram_base; 212 tzdram_end = plat_bl31_params_from_bl2.tzdram_base + 213 plat_bl31_params_from_bl2.tzdram_size; 214 bl32_start = bl32_img_info.image_base; 215 bl32_end = bl32_img_info.image_base + bl32_img_info.image_size; 216 217 assert(tzdram_end > tzdram_start); 218 assert(bl32_end > bl32_start); 219 assert(bl32_image_ep_info.pc > tzdram_start); 220 assert(bl32_image_ep_info.pc < tzdram_end); 221 222 /* relocate BL32 */ 223 if ((bl32_start >= tzdram_end) || (bl32_end <= tzdram_start)) { 224 225 INFO("Relocate BL32 to TZDRAM\n"); 226 227 (void)memcpy16((void *)(uintptr_t)bl32_image_ep_info.pc, 228 (void *)(uintptr_t)bl32_start, 229 bl32_img_info.image_size); 230 231 /* clean up non-secure intermediate buffer */ 232 zeromem((void *)(uintptr_t)bl32_start, 233 bl32_img_info.image_size); 234 } 235 } 236 237 /* 238 * Add timestamp for platform early setup exit. 239 */ 240 boot_profiler_add_record("[TF] early setup exit"); 241 242 INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", 243 (((read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK) 244 == DENVER_IMPL) ? "Denver" : "ARM", read_mpidr()); 245 } 246 247 #ifdef SPD_trusty 248 void plat_trusty_set_boot_args(aapcs64_params_t *args) 249 { 250 /* 251 * arg0 = TZDRAM aperture available for BL32 252 * arg1 = BL32 boot params 253 * arg2 = EKS Blob Length 254 * arg3 = Boot Profiler Carveout Base 255 */ 256 args->arg0 = bl32_args.arg0; 257 args->arg1 = bl32_args.arg2; 258 259 /* update EKS size */ 260 args->arg2 = bl32_args.arg4; 261 262 /* Profiler Carveout Base */ 263 args->arg3 = bl32_args.arg5; 264 } 265 #endif 266 267 /******************************************************************************* 268 * Initialize the gic, configure the SCR. 269 ******************************************************************************/ 270 void bl31_platform_setup(void) 271 { 272 /* 273 * Add timestamp for platform setup entry. 274 */ 275 boot_profiler_add_record("[TF] plat setup entry"); 276 277 /* Initialize the gic cpu and distributor interfaces */ 278 plat_gic_setup(); 279 280 /* 281 * Setup secondary CPU POR infrastructure. 282 */ 283 plat_secondary_setup(); 284 285 /* 286 * Initial Memory Controller configuration. 287 */ 288 tegra_memctrl_setup(); 289 290 /* 291 * Set up the TZRAM memory aperture to allow only secure world 292 * access 293 */ 294 tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE); 295 296 /* 297 * Late setup handler to allow platforms to performs additional 298 * functionality. 299 * This handler gets called with MMU enabled. 300 */ 301 plat_late_platform_setup(); 302 303 /* 304 * Add timestamp for platform setup exit. 305 */ 306 boot_profiler_add_record("[TF] plat setup exit"); 307 308 INFO("BL3-1: Tegra platform setup complete\n"); 309 } 310 311 /******************************************************************************* 312 * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit 313 ******************************************************************************/ 314 void bl31_plat_runtime_setup(void) 315 { 316 /* 317 * During cold boot, it is observed that the arbitration 318 * bit is set in the Memory controller leading to false 319 * error interrupts in the non-secure world. To avoid 320 * this, clean the interrupt status register before 321 * booting into the non-secure world 322 */ 323 tegra_memctrl_clear_pending_interrupts(); 324 325 /* 326 * During boot, USB3 and flash media (SDMMC/SATA) devices need 327 * access to IRAM. Because these clients connect to the MC and 328 * do not have a direct path to the IRAM, the MC implements AHB 329 * redirection during boot to allow path to IRAM. In this mode 330 * accesses to a programmed memory address aperture are directed 331 * to the AHB bus, allowing access to the IRAM. This mode must be 332 * disabled before we jump to the non-secure world. 333 */ 334 tegra_memctrl_disable_ahb_redirection(); 335 336 /* 337 * Add final timestamp before exiting BL31. 338 */ 339 boot_profiler_add_record("[TF] bl31 exit"); 340 boot_profiler_deinit(); 341 } 342 343 /******************************************************************************* 344 * Perform the very early platform specific architectural setup here. At the 345 * moment this only intializes the mmu in a quick and dirty way. 346 ******************************************************************************/ 347 void bl31_plat_arch_setup(void) 348 { 349 uint64_t rw_start = BL31_RW_START; 350 uint64_t rw_size = BL31_RW_END - BL31_RW_START; 351 uint64_t rodata_start = BL31_RODATA_BASE; 352 uint64_t rodata_size = BL31_RODATA_END - BL31_RODATA_BASE; 353 uint64_t code_base = TEXT_START; 354 uint64_t code_size = TEXT_END - TEXT_START; 355 const mmap_region_t *plat_mmio_map = NULL; 356 #if USE_COHERENT_MEM 357 uint32_t coh_start, coh_size; 358 #endif 359 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 360 361 /* 362 * Add timestamp for arch setup entry. 363 */ 364 boot_profiler_add_record("[TF] arch setup entry"); 365 366 /* add MMIO space */ 367 plat_mmio_map = plat_get_mmio_map(); 368 if (plat_mmio_map != NULL) { 369 mmap_add(plat_mmio_map); 370 } else { 371 WARN("MMIO map not available\n"); 372 } 373 374 /* add memory regions */ 375 mmap_add_region(rw_start, rw_start, 376 rw_size, 377 MT_MEMORY | MT_RW | MT_SECURE); 378 mmap_add_region(rodata_start, rodata_start, 379 rodata_size, 380 MT_RO_DATA | MT_SECURE); 381 mmap_add_region(code_base, code_base, 382 code_size, 383 MT_CODE | MT_SECURE); 384 385 #if USE_COHERENT_MEM 386 coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE); 387 coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE; 388 389 mmap_add_region(coh_start, coh_start, 390 coh_size, 391 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE); 392 #endif 393 394 /* map TZDRAM used by BL31 as coherent memory */ 395 if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) { 396 mmap_add_region(params_from_bl2->tzdram_base, 397 params_from_bl2->tzdram_base, 398 BL31_SIZE, 399 MT_DEVICE | MT_RW | MT_SECURE); 400 } 401 402 /* set up translation tables */ 403 init_xlat_tables(); 404 405 /* enable the MMU */ 406 enable_mmu_el3(0); 407 408 /* 409 * Add timestamp for arch setup exit. 410 */ 411 boot_profiler_add_record("[TF] arch setup exit"); 412 413 INFO("BL3-1: Tegra: MMU enabled\n"); 414 } 415 416 /******************************************************************************* 417 * Check if the given NS DRAM range is valid 418 ******************************************************************************/ 419 int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes) 420 { 421 uint64_t end = base + size_in_bytes - U(1); 422 int32_t ret = 0; 423 424 /* 425 * Check if the NS DRAM address is valid 426 */ 427 if ((base < TEGRA_DRAM_BASE) || (base >= TEGRA_DRAM_END) || 428 (end > TEGRA_DRAM_END)) { 429 430 ERROR("NS address 0x%llx is out-of-bounds!\n", base); 431 ret = -EFAULT; 432 } 433 434 /* 435 * TZDRAM aperture contains the BL31 and BL32 images, so we need 436 * to check if the NS DRAM range overlaps the TZDRAM aperture. 437 */ 438 if ((base < (uint64_t)TZDRAM_END) && (end > tegra_bl31_phys_base)) { 439 ERROR("NS address 0x%llx overlaps TZDRAM!\n", base); 440 ret = -ENOTSUP; 441 } 442 443 /* valid NS address */ 444 return ret; 445 } 446