1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <bl31.h> 35 #include <bl_common.h> 36 #include <console.h> 37 #include <cortex_a57.h> 38 #include <cortex_a53.h> 39 #include <debug.h> 40 #include <errno.h> 41 #include <memctrl.h> 42 #include <mmio.h> 43 #include <platform.h> 44 #include <platform_def.h> 45 #include <stddef.h> 46 #include <tegra_private.h> 47 48 /******************************************************************************* 49 * Declarations of linker defined symbols which will help us find the layout 50 * of trusted SRAM 51 ******************************************************************************/ 52 extern unsigned long __RO_START__; 53 extern unsigned long __RO_END__; 54 extern unsigned long __BL31_END__; 55 56 extern uint64_t tegra_bl31_phys_base; 57 58 /* 59 * The next 3 constants identify the extents of the code, RO data region and the 60 * limit of the BL3-1 image. These addresses are used by the MMU setup code and 61 * therefore they must be page-aligned. It is the responsibility of the linker 62 * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols 63 * refer to page-aligned addresses. 64 */ 65 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 66 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 67 #define BL31_END (unsigned long)(&__BL31_END__) 68 69 static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; 70 static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { 71 .tzdram_size = (uint64_t)TZDRAM_SIZE 72 }; 73 74 /******************************************************************************* 75 * This variable holds the non-secure image entry address 76 ******************************************************************************/ 77 extern uint64_t ns_image_entrypoint; 78 79 /******************************************************************************* 80 * Return a pointer to the 'entry_point_info' structure of the next image for 81 * security state specified. BL33 corresponds to the non-secure image type 82 * while BL32 corresponds to the secure image type. 83 ******************************************************************************/ 84 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 85 { 86 if (type == NON_SECURE) 87 return &bl33_image_ep_info; 88 89 if (type == SECURE) 90 return &bl32_image_ep_info; 91 92 return NULL; 93 } 94 95 /******************************************************************************* 96 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image 97 * passes this platform specific information. 98 ******************************************************************************/ 99 plat_params_from_bl2_t *bl31_get_plat_params(void) 100 { 101 return &plat_bl31_params_from_bl2; 102 } 103 104 /******************************************************************************* 105 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image 106 * info. 107 ******************************************************************************/ 108 void bl31_early_platform_setup(bl31_params_t *from_bl2, 109 void *plat_params_from_bl2) 110 { 111 plat_params_from_bl2_t *plat_params = 112 (plat_params_from_bl2_t *)plat_params_from_bl2; 113 114 /* 115 * Configure the UART port to be used as the console 116 */ 117 console_init(TEGRA_BOOT_UART_BASE, TEGRA_BOOT_UART_CLK_IN_HZ, 118 TEGRA_CONSOLE_BAUDRATE); 119 120 /* Initialise crash console */ 121 plat_crash_console_init(); 122 123 /* 124 * Copy BL3-3, BL3-2 entry point information. 125 * They are stored in Secure RAM, in BL2's address space. 126 */ 127 bl33_image_ep_info = *from_bl2->bl33_ep_info; 128 bl32_image_ep_info = *from_bl2->bl32_ep_info; 129 130 /* 131 * Parse platform specific parameters - TZDRAM aperture size 132 */ 133 if (plat_params) 134 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; 135 } 136 137 /******************************************************************************* 138 * Initialize the gic, configure the SCR. 139 ******************************************************************************/ 140 void bl31_platform_setup(void) 141 { 142 uint32_t tmp_reg; 143 144 /* 145 * Initialize delay timer 146 */ 147 tegra_delay_timer_init(); 148 149 /* 150 * Setup secondary CPU POR infrastructure. 151 */ 152 plat_secondary_setup(); 153 154 /* 155 * Initial Memory Controller configuration. 156 */ 157 tegra_memctrl_setup(); 158 159 /* 160 * Do initial security configuration to allow DRAM/device access. 161 */ 162 tegra_memctrl_tzdram_setup(tegra_bl31_phys_base, 163 plat_bl31_params_from_bl2.tzdram_size); 164 165 /* Set the next EL to be AArch64 */ 166 tmp_reg = SCR_RES1_BITS | SCR_RW_BIT; 167 write_scr(tmp_reg); 168 169 /* Initialize the gic cpu and distributor interfaces */ 170 tegra_gic_setup(); 171 } 172 173 /******************************************************************************* 174 * Perform the very early platform specific architectural setup here. At the 175 * moment this only intializes the mmu in a quick and dirty way. 176 ******************************************************************************/ 177 void bl31_plat_arch_setup(void) 178 { 179 unsigned long bl31_base_pa = tegra_bl31_phys_base; 180 unsigned long total_base = bl31_base_pa; 181 unsigned long total_size = BL32_BASE - BL31_RO_BASE; 182 unsigned long ro_start = bl31_base_pa; 183 unsigned long ro_size = BL31_RO_LIMIT - BL31_RO_BASE; 184 const mmap_region_t *plat_mmio_map = NULL; 185 #if USE_COHERENT_MEM 186 unsigned long coh_start, coh_size; 187 #endif 188 189 /* add memory regions */ 190 mmap_add_region(total_base, total_base, 191 total_size, 192 MT_MEMORY | MT_RW | MT_SECURE); 193 mmap_add_region(ro_start, ro_start, 194 ro_size, 195 MT_MEMORY | MT_RO | MT_SECURE); 196 197 #if USE_COHERENT_MEM 198 coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE); 199 coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE; 200 201 mmap_add_region(coh_start, coh_start, 202 coh_size, 203 MT_DEVICE | MT_RW | MT_SECURE); 204 #endif 205 206 /* add MMIO space */ 207 plat_mmio_map = plat_get_mmio_map(); 208 if (plat_mmio_map) 209 mmap_add(plat_mmio_map); 210 else 211 WARN("MMIO map not available\n"); 212 213 /* set up translation tables */ 214 init_xlat_tables(); 215 216 /* enable the MMU */ 217 enable_mmu_el3(0); 218 } 219 220 /******************************************************************************* 221 * Check if the given NS DRAM range is valid 222 ******************************************************************************/ 223 int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes) 224 { 225 uint64_t end = base + size_in_bytes - 1; 226 227 /* 228 * Check if the NS DRAM address is valid 229 */ 230 if ((base < TEGRA_DRAM_BASE) || (end > TEGRA_DRAM_END) || 231 (base >= end)) { 232 ERROR("NS address is out-of-bounds!\n"); 233 return -EFAULT; 234 } 235 236 /* 237 * TZDRAM aperture contains the BL31 and BL32 images, so we need 238 * to check if the NS DRAM range overlaps the TZDRAM aperture. 239 */ 240 if ((base < TZDRAM_END) && (end > tegra_bl31_phys_base)) { 241 ERROR("NS address overlaps TZDRAM!\n"); 242 return -ENOTSUP; 243 } 244 245 /* valid NS address */ 246 return 0; 247 } 248