1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <bl31.h> 35 #include <bl_common.h> 36 #include <console.h> 37 #include <cortex_a57.h> 38 #include <cortex_a53.h> 39 #include <debug.h> 40 #include <denver.h> 41 #include <errno.h> 42 #include <memctrl.h> 43 #include <mmio.h> 44 #include <platform.h> 45 #include <platform_def.h> 46 #include <stddef.h> 47 #include <tegra_private.h> 48 49 /******************************************************************************* 50 * Declarations of linker defined symbols which will help us find the layout 51 * of trusted SRAM 52 ******************************************************************************/ 53 extern unsigned long __RO_START__; 54 extern unsigned long __RO_END__; 55 extern unsigned long __BL31_END__; 56 57 extern uint64_t tegra_bl31_phys_base; 58 59 /* 60 * The next 3 constants identify the extents of the code, RO data region and the 61 * limit of the BL3-1 image. These addresses are used by the MMU setup code and 62 * therefore they must be page-aligned. It is the responsibility of the linker 63 * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols 64 * refer to page-aligned addresses. 65 */ 66 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 67 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 68 #define BL31_END (unsigned long)(&__BL31_END__) 69 70 static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; 71 static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { 72 .tzdram_size = (uint64_t)TZDRAM_SIZE 73 }; 74 75 /******************************************************************************* 76 * This variable holds the non-secure image entry address 77 ******************************************************************************/ 78 extern uint64_t ns_image_entrypoint; 79 80 /******************************************************************************* 81 * Return a pointer to the 'entry_point_info' structure of the next image for 82 * security state specified. BL33 corresponds to the non-secure image type 83 * while BL32 corresponds to the secure image type. 84 ******************************************************************************/ 85 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 86 { 87 if (type == NON_SECURE) 88 return &bl33_image_ep_info; 89 90 if (type == SECURE) 91 return &bl32_image_ep_info; 92 93 return NULL; 94 } 95 96 /******************************************************************************* 97 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image 98 * passes this platform specific information. 99 ******************************************************************************/ 100 plat_params_from_bl2_t *bl31_get_plat_params(void) 101 { 102 return &plat_bl31_params_from_bl2; 103 } 104 105 /******************************************************************************* 106 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image 107 * info. 108 ******************************************************************************/ 109 void bl31_early_platform_setup(bl31_params_t *from_bl2, 110 void *plat_params_from_bl2) 111 { 112 plat_params_from_bl2_t *plat_params = 113 (plat_params_from_bl2_t *)plat_params_from_bl2; 114 #if DEBUG 115 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 116 #endif 117 /* 118 * Configure the UART port to be used as the console 119 */ 120 console_init(TEGRA_BOOT_UART_BASE, TEGRA_BOOT_UART_CLK_IN_HZ, 121 TEGRA_CONSOLE_BAUDRATE); 122 123 /* Initialise crash console */ 124 plat_crash_console_init(); 125 126 INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", (impl == DENVER_IMPL) ? 127 "Denver" : "ARM", read_mpidr()); 128 129 /* 130 * Copy BL3-3, BL3-2 entry point information. 131 * They are stored in Secure RAM, in BL2's address space. 132 */ 133 if (from_bl2->bl33_ep_info) 134 bl33_image_ep_info = *from_bl2->bl33_ep_info; 135 136 if (from_bl2->bl32_ep_info) 137 bl32_image_ep_info = *from_bl2->bl32_ep_info; 138 139 /* 140 * Parse platform specific parameters - TZDRAM aperture size 141 */ 142 if (plat_params) 143 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; 144 } 145 146 /******************************************************************************* 147 * Initialize the gic, configure the SCR. 148 ******************************************************************************/ 149 void bl31_platform_setup(void) 150 { 151 uint32_t tmp_reg; 152 153 /* 154 * Initialize delay timer 155 */ 156 tegra_delay_timer_init(); 157 158 /* 159 * Setup secondary CPU POR infrastructure. 160 */ 161 plat_secondary_setup(); 162 163 /* 164 * Initial Memory Controller configuration. 165 */ 166 tegra_memctrl_setup(); 167 168 /* 169 * Do initial security configuration to allow DRAM/device access. 170 */ 171 tegra_memctrl_tzdram_setup(tegra_bl31_phys_base, 172 plat_bl31_params_from_bl2.tzdram_size); 173 174 /* Set the next EL to be AArch64 */ 175 tmp_reg = SCR_RES1_BITS | SCR_RW_BIT; 176 write_scr(tmp_reg); 177 178 /* Initialize the gic cpu and distributor interfaces */ 179 tegra_gic_setup(); 180 181 INFO("BL3-1: Tegra platform setup complete\n"); 182 } 183 184 /******************************************************************************* 185 * Perform the very early platform specific architectural setup here. At the 186 * moment this only intializes the mmu in a quick and dirty way. 187 ******************************************************************************/ 188 void bl31_plat_arch_setup(void) 189 { 190 unsigned long bl31_base_pa = tegra_bl31_phys_base; 191 unsigned long total_base = bl31_base_pa; 192 unsigned long total_size = BL32_BASE - BL31_RO_BASE; 193 unsigned long ro_start = bl31_base_pa; 194 unsigned long ro_size = BL31_RO_LIMIT - BL31_RO_BASE; 195 const mmap_region_t *plat_mmio_map = NULL; 196 #if USE_COHERENT_MEM 197 unsigned long coh_start, coh_size; 198 #endif 199 200 /* add memory regions */ 201 mmap_add_region(total_base, total_base, 202 total_size, 203 MT_MEMORY | MT_RW | MT_SECURE); 204 mmap_add_region(ro_start, ro_start, 205 ro_size, 206 MT_MEMORY | MT_RO | MT_SECURE); 207 208 #if USE_COHERENT_MEM 209 coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE); 210 coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE; 211 212 mmap_add_region(coh_start, coh_start, 213 coh_size, 214 MT_DEVICE | MT_RW | MT_SECURE); 215 #endif 216 217 /* add MMIO space */ 218 plat_mmio_map = plat_get_mmio_map(); 219 if (plat_mmio_map) 220 mmap_add(plat_mmio_map); 221 else 222 WARN("MMIO map not available\n"); 223 224 /* set up translation tables */ 225 init_xlat_tables(); 226 227 /* enable the MMU */ 228 enable_mmu_el3(0); 229 230 INFO("BL3-1: Tegra: MMU enabled\n"); 231 } 232 233 /******************************************************************************* 234 * Check if the given NS DRAM range is valid 235 ******************************************************************************/ 236 int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes) 237 { 238 uint64_t end = base + size_in_bytes - 1; 239 240 /* 241 * Check if the NS DRAM address is valid 242 */ 243 if ((base < TEGRA_DRAM_BASE) || (end > TEGRA_DRAM_END) || 244 (base >= end)) { 245 ERROR("NS address is out-of-bounds!\n"); 246 return -EFAULT; 247 } 248 249 /* 250 * TZDRAM aperture contains the BL31 and BL32 images, so we need 251 * to check if the NS DRAM range overlaps the TZDRAM aperture. 252 */ 253 if ((base < TZDRAM_END) && (end > tegra_bl31_phys_base)) { 254 ERROR("NS address overlaps TZDRAM!\n"); 255 return -ENOTSUP; 256 } 257 258 /* valid NS address */ 259 return 0; 260 } 261