1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <bl31.h> 11 #include <bl_common.h> 12 #include <console.h> 13 #include <cortex_a53.h> 14 #include <cortex_a57.h> 15 #include <debug.h> 16 #include <denver.h> 17 #include <errno.h> 18 #include <memctrl.h> 19 #include <mmio.h> 20 #include <platform.h> 21 #include <platform_def.h> 22 #include <stddef.h> 23 #include <string.h> 24 #include <tegra_def.h> 25 #include <tegra_private.h> 26 27 /* length of Trusty's input parameters (in bytes) */ 28 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 29 30 extern void zeromem16(void *mem, unsigned int length); 31 32 /******************************************************************************* 33 * Declarations of linker defined symbols which will help us find the layout 34 * of trusted SRAM 35 ******************************************************************************/ 36 extern unsigned long __TEXT_START__; 37 extern unsigned long __TEXT_END__; 38 extern unsigned long __RW_START__; 39 extern unsigned long __RW_END__; 40 extern unsigned long __RODATA_START__; 41 extern unsigned long __RODATA_END__; 42 extern unsigned long __BL31_END__; 43 44 extern uint64_t tegra_bl31_phys_base; 45 extern uint64_t tegra_console_base; 46 47 /* 48 * The next 3 constants identify the extents of the code, RO data region and the 49 * limit of the BL3-1 image. These addresses are used by the MMU setup code and 50 * therefore they must be page-aligned. It is the responsibility of the linker 51 * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols 52 * refer to page-aligned addresses. 53 */ 54 #define BL31_RW_START (unsigned long)(&__RW_START__) 55 #define BL31_RW_END (unsigned long)(&__RW_END__) 56 #define BL31_RODATA_BASE (unsigned long)(&__RODATA_START__) 57 #define BL31_RODATA_END (unsigned long)(&__RODATA_END__) 58 #define BL31_END (unsigned long)(&__BL31_END__) 59 60 static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; 61 static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { 62 .tzdram_size = (uint64_t)TZDRAM_SIZE 63 }; 64 static unsigned long bl32_mem_size; 65 static unsigned long bl32_boot_params; 66 67 /******************************************************************************* 68 * This variable holds the non-secure image entry address 69 ******************************************************************************/ 70 extern uint64_t ns_image_entrypoint; 71 72 /******************************************************************************* 73 * The following platform setup functions are weakly defined. They 74 * provide typical implementations that will be overridden by a SoC. 75 ******************************************************************************/ 76 #pragma weak plat_early_platform_setup 77 #pragma weak plat_get_bl31_params 78 #pragma weak plat_get_bl31_plat_params 79 80 void plat_early_platform_setup(void) 81 { 82 ; /* do nothing */ 83 } 84 85 bl31_params_t *plat_get_bl31_params(void) 86 { 87 return NULL; 88 } 89 90 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 91 { 92 return NULL; 93 } 94 95 /******************************************************************************* 96 * Return a pointer to the 'entry_point_info' structure of the next image for 97 * security state specified. BL33 corresponds to the non-secure image type 98 * while BL32 corresponds to the secure image type. 99 ******************************************************************************/ 100 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 101 { 102 if (type == NON_SECURE) 103 return &bl33_image_ep_info; 104 105 /* return BL32 entry point info if it is valid */ 106 if (type == SECURE && bl32_image_ep_info.pc) 107 return &bl32_image_ep_info; 108 109 return NULL; 110 } 111 112 /******************************************************************************* 113 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image 114 * passes this platform specific information. 115 ******************************************************************************/ 116 plat_params_from_bl2_t *bl31_get_plat_params(void) 117 { 118 return &plat_bl31_params_from_bl2; 119 } 120 121 /******************************************************************************* 122 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image 123 * info. 124 ******************************************************************************/ 125 void bl31_early_platform_setup(bl31_params_t *from_bl2, 126 void *plat_params_from_bl2) 127 { 128 plat_params_from_bl2_t *plat_params = 129 (plat_params_from_bl2_t *)plat_params_from_bl2; 130 #if LOG_LEVEL >= LOG_LEVEL_INFO 131 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 132 #endif 133 image_info_t bl32_img_info = { {0} }; 134 uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end; 135 136 /* 137 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so 138 * there's no argument to relay from a previous bootloader. Platforms 139 * might use custom ways to get arguments, so provide handlers which 140 * they can override. 141 */ 142 if (from_bl2 == NULL) 143 from_bl2 = plat_get_bl31_params(); 144 if (plat_params == NULL) 145 plat_params = plat_get_bl31_plat_params(); 146 147 /* 148 * Copy BL3-3, BL3-2 entry point information. 149 * They are stored in Secure RAM, in BL2's address space. 150 */ 151 assert(from_bl2); 152 assert(from_bl2->bl33_ep_info); 153 bl33_image_ep_info = *from_bl2->bl33_ep_info; 154 155 if (from_bl2->bl32_ep_info) { 156 bl32_image_ep_info = *from_bl2->bl32_ep_info; 157 bl32_mem_size = from_bl2->bl32_ep_info->args.arg0; 158 bl32_boot_params = from_bl2->bl32_ep_info->args.arg2; 159 } 160 161 /* 162 * Parse platform specific parameters - TZDRAM aperture base and size 163 */ 164 assert(plat_params); 165 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base; 166 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; 167 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id; 168 169 /* 170 * It is very important that we run either from TZDRAM or TZSRAM base. 171 * Add an explicit check here. 172 */ 173 if ((plat_bl31_params_from_bl2.tzdram_base != BL31_BASE) && 174 (TEGRA_TZRAM_BASE != BL31_BASE)) 175 panic(); 176 177 /* 178 * Get the base address of the UART controller to be used for the 179 * console 180 */ 181 tegra_console_base = plat_get_console_from_id(plat_params->uart_id); 182 183 if (tegra_console_base != (uint64_t)0) { 184 /* 185 * Configure the UART port to be used as the console 186 */ 187 console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ, 188 TEGRA_CONSOLE_BAUDRATE); 189 } 190 191 /* 192 * Initialize delay timer 193 */ 194 tegra_delay_timer_init(); 195 196 /* 197 * Do initial security configuration to allow DRAM/device access. 198 */ 199 tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base, 200 plat_bl31_params_from_bl2.tzdram_size); 201 202 /* 203 * The previous bootloader might not have placed the BL32 image 204 * inside the TZDRAM. We check the BL32 image info to find out 205 * the base/PC values and relocate the image if necessary. 206 */ 207 if (from_bl2->bl32_image_info) { 208 209 bl32_img_info = *from_bl2->bl32_image_info; 210 211 /* Relocate BL32 if it resides outside of the TZDRAM */ 212 tzdram_start = plat_bl31_params_from_bl2.tzdram_base; 213 tzdram_end = plat_bl31_params_from_bl2.tzdram_base + 214 plat_bl31_params_from_bl2.tzdram_size; 215 bl32_start = bl32_img_info.image_base; 216 bl32_end = bl32_img_info.image_base + bl32_img_info.image_size; 217 218 assert(tzdram_end > tzdram_start); 219 assert(bl32_end > bl32_start); 220 assert(bl32_image_ep_info.pc > tzdram_start); 221 assert(bl32_image_ep_info.pc < tzdram_end); 222 223 /* relocate BL32 */ 224 if (bl32_start >= tzdram_end || bl32_end <= tzdram_start) { 225 226 INFO("Relocate BL32 to TZDRAM\n"); 227 228 memcpy16((void *)(uintptr_t)bl32_image_ep_info.pc, 229 (void *)(uintptr_t)bl32_start, 230 bl32_img_info.image_size); 231 232 /* clean up non-secure intermediate buffer */ 233 zeromem16((void *)(uintptr_t)bl32_start, 234 bl32_img_info.image_size); 235 } 236 } 237 238 /* Early platform setup for Tegra SoCs */ 239 plat_early_platform_setup(); 240 241 INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", (impl == DENVER_IMPL) ? 242 "Denver" : "ARM", read_mpidr()); 243 } 244 245 #ifdef SPD_trusty 246 void plat_trusty_set_boot_args(aapcs64_params_t *args) 247 { 248 args->arg0 = bl32_mem_size; 249 args->arg1 = bl32_boot_params; 250 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 251 } 252 #endif 253 254 /******************************************************************************* 255 * Initialize the gic, configure the SCR. 256 ******************************************************************************/ 257 void bl31_platform_setup(void) 258 { 259 uint32_t tmp_reg; 260 261 /* Initialize the gic cpu and distributor interfaces */ 262 plat_gic_setup(); 263 264 /* 265 * Setup secondary CPU POR infrastructure. 266 */ 267 plat_secondary_setup(); 268 269 /* 270 * Initial Memory Controller configuration. 271 */ 272 tegra_memctrl_setup(); 273 274 /* 275 * Set up the TZRAM memory aperture to allow only secure world 276 * access 277 */ 278 tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE); 279 280 /* Set the next EL to be AArch64 */ 281 tmp_reg = SCR_RES1_BITS | SCR_RW_BIT; 282 write_scr(tmp_reg); 283 284 INFO("BL3-1: Tegra platform setup complete\n"); 285 } 286 287 /******************************************************************************* 288 * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit 289 ******************************************************************************/ 290 void bl31_plat_runtime_setup(void) 291 { 292 /* 293 * During boot, USB3 and flash media (SDMMC/SATA) devices need 294 * access to IRAM. Because these clients connect to the MC and 295 * do not have a direct path to the IRAM, the MC implements AHB 296 * redirection during boot to allow path to IRAM. In this mode 297 * accesses to a programmed memory address aperture are directed 298 * to the AHB bus, allowing access to the IRAM. This mode must be 299 * disabled before we jump to the non-secure world. 300 */ 301 tegra_memctrl_disable_ahb_redirection(); 302 } 303 304 /******************************************************************************* 305 * Perform the very early platform specific architectural setup here. At the 306 * moment this only intializes the mmu in a quick and dirty way. 307 ******************************************************************************/ 308 void bl31_plat_arch_setup(void) 309 { 310 unsigned long rw_start = BL31_RW_START; 311 unsigned long rw_size = BL31_RW_END - BL31_RW_START; 312 unsigned long rodata_start = BL31_RODATA_BASE; 313 unsigned long rodata_size = BL31_RODATA_END - BL31_RODATA_BASE; 314 unsigned long code_base = (unsigned long)(&__TEXT_START__); 315 unsigned long code_size = (unsigned long)(&__TEXT_END__) - code_base; 316 const mmap_region_t *plat_mmio_map = NULL; 317 #if USE_COHERENT_MEM 318 unsigned long coh_start, coh_size; 319 #endif 320 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 321 322 /* add memory regions */ 323 mmap_add_region(rw_start, rw_start, 324 rw_size, 325 MT_MEMORY | MT_RW | MT_SECURE); 326 mmap_add_region(rodata_start, rodata_start, 327 rodata_size, 328 MT_RO_DATA | MT_SECURE); 329 mmap_add_region(code_base, code_base, 330 code_size, 331 MT_CODE | MT_SECURE); 332 333 /* map TZDRAM used by BL31 as coherent memory */ 334 if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) { 335 mmap_add_region(params_from_bl2->tzdram_base, 336 params_from_bl2->tzdram_base, 337 BL31_SIZE, 338 MT_DEVICE | MT_RW | MT_SECURE); 339 } 340 341 #if USE_COHERENT_MEM 342 coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE); 343 coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE; 344 345 mmap_add_region(coh_start, coh_start, 346 coh_size, 347 MT_DEVICE | MT_RW | MT_SECURE); 348 #endif 349 350 /* map on-chip free running uS timer */ 351 mmap_add_region(page_align((uint64_t)TEGRA_TMRUS_BASE, 0), 352 page_align((uint64_t)TEGRA_TMRUS_BASE, 0), 353 (uint64_t)TEGRA_TMRUS_SIZE, 354 MT_DEVICE | MT_RO | MT_SECURE); 355 356 /* add MMIO space */ 357 plat_mmio_map = plat_get_mmio_map(); 358 if (plat_mmio_map) 359 mmap_add(plat_mmio_map); 360 else 361 WARN("MMIO map not available\n"); 362 363 /* set up translation tables */ 364 init_xlat_tables(); 365 366 /* enable the MMU */ 367 enable_mmu_el3(0); 368 369 INFO("BL3-1: Tegra: MMU enabled\n"); 370 } 371 372 /******************************************************************************* 373 * Check if the given NS DRAM range is valid 374 ******************************************************************************/ 375 int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes) 376 { 377 uint64_t end = base + size_in_bytes; 378 379 /* 380 * Check if the NS DRAM address is valid 381 */ 382 if ((base < TEGRA_DRAM_BASE) || (end > TEGRA_DRAM_END)) { 383 ERROR("NS address is out-of-bounds!\n"); 384 return -EFAULT; 385 } 386 387 /* 388 * TZDRAM aperture contains the BL31 and BL32 images, so we need 389 * to check if the NS DRAM range overlaps the TZDRAM aperture. 390 */ 391 if ((base < TZDRAM_END) && (end > tegra_bl31_phys_base)) { 392 ERROR("NS address overlaps TZDRAM!\n"); 393 return -ENOTSUP; 394 } 395 396 /* valid NS address */ 397 return 0; 398 } 399