108438e24SVarun Wadekar/* 208438e24SVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 408438e24SVarun Wadekar * Redistribution and use in source and binary forms, with or without 508438e24SVarun Wadekar * modification, are permitted provided that the following conditions are met: 608438e24SVarun Wadekar * 708438e24SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 808438e24SVarun Wadekar * list of conditions and the following disclaimer. 908438e24SVarun Wadekar * 1008438e24SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 1108438e24SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 1208438e24SVarun Wadekar * and/or other materials provided with the distribution. 1308438e24SVarun Wadekar * 1408438e24SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 1508438e24SVarun Wadekar * to endorse or promote products derived from this software without specific 1608438e24SVarun Wadekar * prior written permission. 1708438e24SVarun Wadekar * 1808438e24SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 1908438e24SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2008438e24SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2108438e24SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2208438e24SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2308438e24SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2408438e24SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2508438e24SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2608438e24SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2708438e24SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 2808438e24SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 2908438e24SVarun Wadekar */ 3008438e24SVarun Wadekar#include <arch.h> 3108438e24SVarun Wadekar#include <asm_macros.S> 3208438e24SVarun Wadekar#include <assert_macros.S> 3308438e24SVarun Wadekar#include <cpu_macros.S> 3408438e24SVarun Wadekar#include <cortex_a57.h> 3508438e24SVarun Wadekar#include <cortex_a53.h> 3611bd24beSVarun Wadekar#include <platform_def.h> 3708438e24SVarun Wadekar#include <tegra_def.h> 3808438e24SVarun Wadekar 390cd6138dSVarun Wadekar#define MIDR_PN_CORTEX_A57 0xD07 400cd6138dSVarun Wadekar 410cd6138dSVarun Wadekar/******************************************************************************* 420cd6138dSVarun Wadekar * Implementation defined ACTLR_EL3 bit definitions 430cd6138dSVarun Wadekar ******************************************************************************/ 440cd6138dSVarun Wadekar#define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 450cd6138dSVarun Wadekar#define ACTLR_EL3_L2ECTLR_BIT (1 << 5) 460cd6138dSVarun Wadekar#define ACTLR_EL3_L2CTLR_BIT (1 << 4) 470cd6138dSVarun Wadekar#define ACTLR_EL3_CPUECTLR_BIT (1 << 1) 480cd6138dSVarun Wadekar#define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 490cd6138dSVarun Wadekar#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ 500cd6138dSVarun Wadekar ACTLR_EL3_L2ECTLR_BIT | \ 510cd6138dSVarun Wadekar ACTLR_EL3_L2CTLR_BIT | \ 520cd6138dSVarun Wadekar ACTLR_EL3_CPUECTLR_BIT | \ 530cd6138dSVarun Wadekar ACTLR_EL3_CPUACTLR_BIT) 540cd6138dSVarun Wadekar 5508438e24SVarun Wadekar /* Global functions */ 5671cb26eaSVarun Wadekar .globl plat_is_my_cpu_primary 5771cb26eaSVarun Wadekar .globl plat_my_core_pos 5871cb26eaSVarun Wadekar .globl plat_get_my_entrypoint 5908438e24SVarun Wadekar .globl plat_secondary_cold_boot_setup 6008438e24SVarun Wadekar .globl platform_mem_init 6108438e24SVarun Wadekar .globl plat_crash_console_init 6208438e24SVarun Wadekar .globl plat_crash_console_putc 6308438e24SVarun Wadekar .globl tegra_secure_entrypoint 6408438e24SVarun Wadekar .globl plat_reset_handler 6508438e24SVarun Wadekar 6608438e24SVarun Wadekar /* Global variables */ 6771cb26eaSVarun Wadekar .globl tegra_sec_entry_point 6808438e24SVarun Wadekar .globl ns_image_entrypoint 6908438e24SVarun Wadekar .globl tegra_bl31_phys_base 70e1084216SVarun Wadekar .globl tegra_console_base 71018b8480SVarun Wadekar .globl tegra_enable_l2_ecc_parity_prot 7208438e24SVarun Wadekar 7308438e24SVarun Wadekar /* --------------------- 7408438e24SVarun Wadekar * Common CPU init code 7508438e24SVarun Wadekar * --------------------- 7608438e24SVarun Wadekar */ 7708438e24SVarun Wadekar.macro cpu_init_common 7808438e24SVarun Wadekar 790cd6138dSVarun Wadekar /* ------------------------------------------------ 80018b8480SVarun Wadekar * We enable procesor retention, L2/CPUECTLR NS 81018b8480SVarun Wadekar * access and ECC/Parity protection for A57 CPUs 820cd6138dSVarun Wadekar * ------------------------------------------------ 830cd6138dSVarun Wadekar */ 840cd6138dSVarun Wadekar mrs x0, midr_el1 850cd6138dSVarun Wadekar mov x1, #(MIDR_PN_MASK << MIDR_PN_SHIFT) 860cd6138dSVarun Wadekar and x0, x0, x1 870cd6138dSVarun Wadekar lsr x0, x0, #MIDR_PN_SHIFT 880cd6138dSVarun Wadekar cmp x0, #MIDR_PN_CORTEX_A57 890cd6138dSVarun Wadekar b.ne 1f 900cd6138dSVarun Wadekar 91b42192bcSVarun Wadekar /* --------------------------- 92b42192bcSVarun Wadekar * Enable processor retention 93b42192bcSVarun Wadekar * --------------------------- 94b42192bcSVarun Wadekar */ 95b42192bcSVarun Wadekar mrs x0, L2ECTLR_EL1 96b42192bcSVarun Wadekar mov x1, #RETENTION_ENTRY_TICKS_512 << L2ECTLR_RET_CTRL_SHIFT 97b42192bcSVarun Wadekar bic x0, x0, #L2ECTLR_RET_CTRL_MASK 98b42192bcSVarun Wadekar orr x0, x0, x1 99b42192bcSVarun Wadekar msr L2ECTLR_EL1, x0 100b42192bcSVarun Wadekar isb 101b42192bcSVarun Wadekar 102b42192bcSVarun Wadekar mrs x0, CPUECTLR_EL1 103b42192bcSVarun Wadekar mov x1, #RETENTION_ENTRY_TICKS_512 << CPUECTLR_CPU_RET_CTRL_SHIFT 104b42192bcSVarun Wadekar bic x0, x0, #CPUECTLR_CPU_RET_CTRL_MASK 105b42192bcSVarun Wadekar orr x0, x0, x1 106b42192bcSVarun Wadekar msr CPUECTLR_EL1, x0 107b42192bcSVarun Wadekar isb 108b42192bcSVarun Wadekar 10908438e24SVarun Wadekar /* ------------------------------------------------------- 11008438e24SVarun Wadekar * Enable L2 and CPU ECTLR RW access from non-secure world 11108438e24SVarun Wadekar * ------------------------------------------------------- 11208438e24SVarun Wadekar */ 11308438e24SVarun Wadekar mov x0, #ACTLR_EL3_ENABLE_ALL_ACCESS 11408438e24SVarun Wadekar msr actlr_el3, x0 11508438e24SVarun Wadekar msr actlr_el2, x0 11608438e24SVarun Wadekar isb 11708438e24SVarun Wadekar 118018b8480SVarun Wadekar /* ------------------------------------------------------- 119018b8480SVarun Wadekar * Enable L2 ECC and Parity Protection 120018b8480SVarun Wadekar * ------------------------------------------------------- 121018b8480SVarun Wadekar */ 122018b8480SVarun Wadekar adr x0, tegra_enable_l2_ecc_parity_prot 123018b8480SVarun Wadekar ldr x0, [x0] 124018b8480SVarun Wadekar cbz x0, 1f 125018b8480SVarun Wadekar mrs x0, L2CTLR_EL1 126018b8480SVarun Wadekar and x1, x0, #L2_ECC_PARITY_PROTECTION_BIT 127018b8480SVarun Wadekar cbnz x1, 1f 128018b8480SVarun Wadekar orr x0, x0, #L2_ECC_PARITY_PROTECTION_BIT 129018b8480SVarun Wadekar msr L2CTLR_EL1, x0 130018b8480SVarun Wadekar isb 131018b8480SVarun Wadekar 13208438e24SVarun Wadekar /* -------------------------------- 13308438e24SVarun Wadekar * Enable the cycle count register 13408438e24SVarun Wadekar * -------------------------------- 13508438e24SVarun Wadekar */ 1360cd6138dSVarun Wadekar1: mrs x0, pmcr_el0 13708438e24SVarun Wadekar ubfx x0, x0, #11, #5 // read PMCR.N field 13808438e24SVarun Wadekar mov x1, #1 13908438e24SVarun Wadekar lsl x0, x1, x0 14008438e24SVarun Wadekar sub x0, x0, #1 // mask of event counters 14108438e24SVarun Wadekar orr x0, x0, #0x80000000 // disable overflow intrs 14208438e24SVarun Wadekar msr pmintenclr_el1, x0 14308438e24SVarun Wadekar msr pmuserenr_el0, x1 // enable user mode access 14408438e24SVarun Wadekar 14508438e24SVarun Wadekar /* ---------------------------------------------------------------- 14608438e24SVarun Wadekar * Allow non-privileged access to CNTVCT: Set CNTKCTL (Kernel Count 14708438e24SVarun Wadekar * register), bit 1 (EL0VCTEN) to enable access to CNTVCT/CNTFRQ 14808438e24SVarun Wadekar * registers from EL0. 14908438e24SVarun Wadekar * ---------------------------------------------------------------- 15008438e24SVarun Wadekar */ 15108438e24SVarun Wadekar mrs x0, cntkctl_el1 15208438e24SVarun Wadekar orr x0, x0, #EL0VCTEN_BIT 15308438e24SVarun Wadekar msr cntkctl_el1, x0 15408438e24SVarun Wadekar.endm 15508438e24SVarun Wadekar 15608438e24SVarun Wadekar /* ----------------------------------------------------- 15771cb26eaSVarun Wadekar * unsigned int plat_is_my_cpu_primary(void); 15808438e24SVarun Wadekar * 15908438e24SVarun Wadekar * This function checks if this is the Primary CPU 16008438e24SVarun Wadekar * ----------------------------------------------------- 16108438e24SVarun Wadekar */ 16271cb26eaSVarun Wadekarfunc plat_is_my_cpu_primary 16371cb26eaSVarun Wadekar mrs x0, mpidr_el1 16408438e24SVarun Wadekar and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 16508438e24SVarun Wadekar cmp x0, #TEGRA_PRIMARY_CPU 16608438e24SVarun Wadekar cset x0, eq 16708438e24SVarun Wadekar ret 16871cb26eaSVarun Wadekarendfunc plat_is_my_cpu_primary 16908438e24SVarun Wadekar 17008438e24SVarun Wadekar /* ----------------------------------------------------- 17171cb26eaSVarun Wadekar * unsigned int plat_my_core_pos(void); 17208438e24SVarun Wadekar * 17371cb26eaSVarun Wadekar * result: CorePos = CoreId + (ClusterId << 2) 17408438e24SVarun Wadekar * ----------------------------------------------------- 17508438e24SVarun Wadekar */ 17671cb26eaSVarun Wadekarfunc plat_my_core_pos 17771cb26eaSVarun Wadekar mrs x0, mpidr_el1 17871cb26eaSVarun Wadekar and x1, x0, #MPIDR_CPU_MASK 17971cb26eaSVarun Wadekar and x0, x0, #MPIDR_CLUSTER_MASK 18071cb26eaSVarun Wadekar add x0, x1, x0, LSR #6 18108438e24SVarun Wadekar ret 18271cb26eaSVarun Wadekarendfunc plat_my_core_pos 18371cb26eaSVarun Wadekar 18471cb26eaSVarun Wadekar /* ----------------------------------------------------- 18571cb26eaSVarun Wadekar * unsigned long plat_get_my_entrypoint (void); 18671cb26eaSVarun Wadekar * 18771cb26eaSVarun Wadekar * Main job of this routine is to distinguish between 18871cb26eaSVarun Wadekar * a cold and warm boot. If the tegra_sec_entry_point for 18971cb26eaSVarun Wadekar * this CPU is present, then it's a warm boot. 19071cb26eaSVarun Wadekar * 19171cb26eaSVarun Wadekar * ----------------------------------------------------- 19271cb26eaSVarun Wadekar */ 19371cb26eaSVarun Wadekarfunc plat_get_my_entrypoint 19471cb26eaSVarun Wadekar adr x1, tegra_sec_entry_point 19571cb26eaSVarun Wadekar ldr x0, [x1] 19671cb26eaSVarun Wadekar ret 19771cb26eaSVarun Wadekarendfunc plat_get_my_entrypoint 19808438e24SVarun Wadekar 19908438e24SVarun Wadekar /* ----------------------------------------------------- 200bde81dccSVarun Wadekar * int platform_get_core_pos(int mpidr); 201bde81dccSVarun Wadekar * 202bde81dccSVarun Wadekar * With this function: CorePos = (ClusterId * 4) + 203bde81dccSVarun Wadekar * CoreId 204bde81dccSVarun Wadekar * ----------------------------------------------------- 205bde81dccSVarun Wadekar */ 206bde81dccSVarun Wadekarfunc platform_get_core_pos 207bde81dccSVarun Wadekar and x1, x0, #MPIDR_CPU_MASK 208bde81dccSVarun Wadekar and x0, x0, #MPIDR_CLUSTER_MASK 209bde81dccSVarun Wadekar add x0, x1, x0, LSR #6 210bde81dccSVarun Wadekar ret 211bde81dccSVarun Wadekarendfunc platform_get_core_pos 212bde81dccSVarun Wadekar 213bde81dccSVarun Wadekar /* ----------------------------------------------------- 21408438e24SVarun Wadekar * void plat_secondary_cold_boot_setup (void); 21508438e24SVarun Wadekar * 21608438e24SVarun Wadekar * This function performs any platform specific actions 21708438e24SVarun Wadekar * needed for a secondary cpu after a cold reset. Right 21808438e24SVarun Wadekar * now this is a stub function. 21908438e24SVarun Wadekar * ----------------------------------------------------- 22008438e24SVarun Wadekar */ 22108438e24SVarun Wadekarfunc plat_secondary_cold_boot_setup 22208438e24SVarun Wadekar mov x0, #0 22308438e24SVarun Wadekar ret 22408438e24SVarun Wadekarendfunc plat_secondary_cold_boot_setup 22508438e24SVarun Wadekar 22608438e24SVarun Wadekar /* -------------------------------------------------------- 22708438e24SVarun Wadekar * void platform_mem_init (void); 22808438e24SVarun Wadekar * 22908438e24SVarun Wadekar * Any memory init, relocation to be done before the 23008438e24SVarun Wadekar * platform boots. Called very early in the boot process. 23108438e24SVarun Wadekar * -------------------------------------------------------- 23208438e24SVarun Wadekar */ 23308438e24SVarun Wadekarfunc platform_mem_init 23408438e24SVarun Wadekar mov x0, #0 23508438e24SVarun Wadekar ret 23608438e24SVarun Wadekarendfunc platform_mem_init 23708438e24SVarun Wadekar 23808438e24SVarun Wadekar /* --------------------------------------------- 23908438e24SVarun Wadekar * int plat_crash_console_init(void) 24008438e24SVarun Wadekar * Function to initialize the crash console 24108438e24SVarun Wadekar * without a C Runtime to print crash report. 2429400b40eSJuan Castillo * Clobber list : x0 - x4 24308438e24SVarun Wadekar * --------------------------------------------- 24408438e24SVarun Wadekar */ 24508438e24SVarun Wadekarfunc plat_crash_console_init 246*e87dac6bSVarun Wadekar mov x0, #0 247*e87dac6bSVarun Wadekar adr x1, tegra_console_base 248*e87dac6bSVarun Wadekar ldr x1, [x1] 249*e87dac6bSVarun Wadekar cbz x1, 1f 250*e87dac6bSVarun Wadekar mov w0, #1 251*e87dac6bSVarun Wadekar1: ret 25208438e24SVarun Wadekarendfunc plat_crash_console_init 25308438e24SVarun Wadekar 25408438e24SVarun Wadekar /* --------------------------------------------- 25508438e24SVarun Wadekar * int plat_crash_console_putc(void) 25608438e24SVarun Wadekar * Function to print a character on the crash 25708438e24SVarun Wadekar * console without a C Runtime. 25808438e24SVarun Wadekar * Clobber list : x1, x2 25908438e24SVarun Wadekar * --------------------------------------------- 26008438e24SVarun Wadekar */ 26108438e24SVarun Wadekarfunc plat_crash_console_putc 262e1084216SVarun Wadekar adr x1, tegra_console_base 263e1084216SVarun Wadekar ldr x1, [x1] 26408438e24SVarun Wadekar b console_core_putc 26508438e24SVarun Wadekarendfunc plat_crash_console_putc 26608438e24SVarun Wadekar 26708438e24SVarun Wadekar /* --------------------------------------------------- 26808438e24SVarun Wadekar * Function to handle a platform reset and store 26908438e24SVarun Wadekar * input parameters passed by BL2. 27008438e24SVarun Wadekar * --------------------------------------------------- 27108438e24SVarun Wadekar */ 27208438e24SVarun Wadekarfunc plat_reset_handler 27308438e24SVarun Wadekar 274939dcf25SVarun Wadekar /* ---------------------------------------------------- 275939dcf25SVarun Wadekar * Verify if we are running from BL31_BASE address 276939dcf25SVarun Wadekar * ---------------------------------------------------- 277939dcf25SVarun Wadekar */ 278939dcf25SVarun Wadekar adr x18, bl31_entrypoint 279939dcf25SVarun Wadekar mov x17, #BL31_BASE 280939dcf25SVarun Wadekar cmp x18, x17 281939dcf25SVarun Wadekar b.eq 1f 282939dcf25SVarun Wadekar 283939dcf25SVarun Wadekar /* ---------------------------------------------------- 284939dcf25SVarun Wadekar * Copy the entire BL31 code to BL31_BASE if we are not 285939dcf25SVarun Wadekar * running from it already 286939dcf25SVarun Wadekar * ---------------------------------------------------- 287939dcf25SVarun Wadekar */ 288939dcf25SVarun Wadekar mov x0, x17 289939dcf25SVarun Wadekar mov x1, x18 290939dcf25SVarun Wadekar mov x2, #BL31_SIZE 291939dcf25SVarun Wadekar_loop16: 292939dcf25SVarun Wadekar cmp x2, #16 293768baf6eSDouglas Raillard b.lo _loop1 294939dcf25SVarun Wadekar ldp x3, x4, [x1], #16 295939dcf25SVarun Wadekar stp x3, x4, [x0], #16 296939dcf25SVarun Wadekar sub x2, x2, #16 297939dcf25SVarun Wadekar b _loop16 298939dcf25SVarun Wadekar /* copy byte per byte */ 299939dcf25SVarun Wadekar_loop1: 300939dcf25SVarun Wadekar cbz x2, _end 301939dcf25SVarun Wadekar ldrb w3, [x1], #1 302939dcf25SVarun Wadekar strb w3, [x0], #1 303939dcf25SVarun Wadekar subs x2, x2, #1 304939dcf25SVarun Wadekar b.ne _loop1 305939dcf25SVarun Wadekar 306939dcf25SVarun Wadekar /* ---------------------------------------------------- 307939dcf25SVarun Wadekar * Jump to BL31_BASE and start execution again 308939dcf25SVarun Wadekar * ---------------------------------------------------- 309939dcf25SVarun Wadekar */ 310939dcf25SVarun Wadekar_end: mov x0, x20 311939dcf25SVarun Wadekar mov x1, x21 312939dcf25SVarun Wadekar br x17 313939dcf25SVarun Wadekar1: 314939dcf25SVarun Wadekar 31508438e24SVarun Wadekar /* ----------------------------------- 31608438e24SVarun Wadekar * derive and save the phys_base addr 31708438e24SVarun Wadekar * ----------------------------------- 31808438e24SVarun Wadekar */ 31908438e24SVarun Wadekar adr x17, tegra_bl31_phys_base 32008438e24SVarun Wadekar ldr x18, [x17] 32108438e24SVarun Wadekar cbnz x18, 1f 32208438e24SVarun Wadekar adr x18, bl31_entrypoint 32308438e24SVarun Wadekar str x18, [x17] 32408438e24SVarun Wadekar 32508438e24SVarun Wadekar1: cpu_init_common 32608438e24SVarun Wadekar 32708438e24SVarun Wadekar ret 32808438e24SVarun Wadekarendfunc plat_reset_handler 32908438e24SVarun Wadekar 33008438e24SVarun Wadekar /* ---------------------------------------- 33108438e24SVarun Wadekar * Secure entrypoint function for CPU boot 33208438e24SVarun Wadekar * ---------------------------------------- 33308438e24SVarun Wadekar */ 33408438e24SVarun Wadekar .align 6 33508438e24SVarun Wadekarfunc tegra_secure_entrypoint 33608438e24SVarun Wadekar 33708438e24SVarun Wadekar#if ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT 33808438e24SVarun Wadekar 33908438e24SVarun Wadekar /* ------------------------------------------------------- 34008438e24SVarun Wadekar * Invalidate BTB along with I$ to remove any stale 34108438e24SVarun Wadekar * entries from the branch predictor array. 34208438e24SVarun Wadekar * ------------------------------------------------------- 34308438e24SVarun Wadekar */ 34408438e24SVarun Wadekar mrs x0, CPUACTLR_EL1 34508438e24SVarun Wadekar orr x0, x0, #1 34608438e24SVarun Wadekar msr CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */ 34708438e24SVarun Wadekar dsb sy 34808438e24SVarun Wadekar isb 34908438e24SVarun Wadekar ic iallu /* actual invalidate */ 35008438e24SVarun Wadekar dsb sy 35108438e24SVarun Wadekar isb 35208438e24SVarun Wadekar 35308438e24SVarun Wadekar mrs x0, CPUACTLR_EL1 35408438e24SVarun Wadekar bic x0, x0, #1 35508438e24SVarun Wadekar msr CPUACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */ 35608438e24SVarun Wadekar dsb sy 35708438e24SVarun Wadekar isb 35808438e24SVarun Wadekar 35908438e24SVarun Wadekar .rept 7 36008438e24SVarun Wadekar nop /* wait */ 36108438e24SVarun Wadekar .endr 36208438e24SVarun Wadekar 36308438e24SVarun Wadekar /* ----------------------------------------------- 36408438e24SVarun Wadekar * Extract OSLK bit and check if it is '1'. This 36508438e24SVarun Wadekar * bit remains '0' for A53 on warm-resets. If '1', 36608438e24SVarun Wadekar * turn off regional clock gating and request warm 36708438e24SVarun Wadekar * reset. 36808438e24SVarun Wadekar * ----------------------------------------------- 36908438e24SVarun Wadekar */ 37008438e24SVarun Wadekar mrs x0, oslsr_el1 37108438e24SVarun Wadekar and x0, x0, #2 37208438e24SVarun Wadekar mrs x1, mpidr_el1 37308438e24SVarun Wadekar bics xzr, x0, x1, lsr #7 /* 0 = slow cluster or warm reset */ 37408438e24SVarun Wadekar b.eq restore_oslock 37508438e24SVarun Wadekar mov x0, xzr 37608438e24SVarun Wadekar msr oslar_el1, x0 /* os lock stays 0 across warm reset */ 37708438e24SVarun Wadekar mov x3, #3 37808438e24SVarun Wadekar movz x4, #0x8000, lsl #48 37908438e24SVarun Wadekar msr CPUACTLR_EL1, x4 /* turn off RCG */ 38008438e24SVarun Wadekar isb 38108438e24SVarun Wadekar msr rmr_el3, x3 /* request warm reset */ 38208438e24SVarun Wadekar isb 38308438e24SVarun Wadekar dsb sy 38408438e24SVarun Wadekar1: wfi 38508438e24SVarun Wadekar b 1b 38608438e24SVarun Wadekar 38708438e24SVarun Wadekar /* -------------------------------------------------- 38808438e24SVarun Wadekar * These nops are here so that speculative execution 38908438e24SVarun Wadekar * won't harm us before we are done with warm reset. 39008438e24SVarun Wadekar * -------------------------------------------------- 39108438e24SVarun Wadekar */ 39208438e24SVarun Wadekar .rept 65 39308438e24SVarun Wadekar nop 39408438e24SVarun Wadekar .endr 39508438e24SVarun Wadekar 39608438e24SVarun Wadekar /* -------------------------------------------------- 39708438e24SVarun Wadekar * Do not insert instructions here 39808438e24SVarun Wadekar * -------------------------------------------------- 39908438e24SVarun Wadekar */ 40008438e24SVarun Wadekar#endif 40108438e24SVarun Wadekar 40208438e24SVarun Wadekar /* -------------------------------------------------- 40308438e24SVarun Wadekar * Restore OS Lock bit 40408438e24SVarun Wadekar * -------------------------------------------------- 40508438e24SVarun Wadekar */ 40608438e24SVarun Wadekarrestore_oslock: 40708438e24SVarun Wadekar mov x0, #1 40808438e24SVarun Wadekar msr oslar_el1, x0 40908438e24SVarun Wadekar 41008438e24SVarun Wadekar cpu_init_common 41108438e24SVarun Wadekar 41208438e24SVarun Wadekar /* --------------------------------------------------------------------- 41308438e24SVarun Wadekar * The initial state of the Architectural feature trap register 41408438e24SVarun Wadekar * (CPTR_EL3) is unknown and it must be set to a known state. All 41508438e24SVarun Wadekar * feature traps are disabled. Some bits in this register are marked as 41608438e24SVarun Wadekar * Reserved and should not be modified. 41708438e24SVarun Wadekar * 41808438e24SVarun Wadekar * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1 41908438e24SVarun Wadekar * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2. 42008438e24SVarun Wadekar * CPTR_EL3.TTA: This causes access to the Trace functionality to trap 42108438e24SVarun Wadekar * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register 42208438e24SVarun Wadekar * access to trace functionality is not supported, this bit is RES0. 42308438e24SVarun Wadekar * CPTR_EL3.TFP: This causes instructions that access the registers 42408438e24SVarun Wadekar * associated with Floating Point and Advanced SIMD execution to trap 42508438e24SVarun Wadekar * to EL3 when executed from any exception level, unless trapped to EL1 42608438e24SVarun Wadekar * or EL2. 42708438e24SVarun Wadekar * --------------------------------------------------------------------- 42808438e24SVarun Wadekar */ 42908438e24SVarun Wadekar mrs x1, cptr_el3 43008438e24SVarun Wadekar bic w1, w1, #TCPAC_BIT 43108438e24SVarun Wadekar bic w1, w1, #TTA_BIT 43208438e24SVarun Wadekar bic w1, w1, #TFP_BIT 43308438e24SVarun Wadekar msr cptr_el3, x1 43408438e24SVarun Wadekar 43508438e24SVarun Wadekar /* -------------------------------------------------- 43608438e24SVarun Wadekar * Get secure world's entry point and jump to it 43708438e24SVarun Wadekar * -------------------------------------------------- 43808438e24SVarun Wadekar */ 43971cb26eaSVarun Wadekar bl plat_get_my_entrypoint 44008438e24SVarun Wadekar br x0 44108438e24SVarun Wadekarendfunc tegra_secure_entrypoint 44208438e24SVarun Wadekar 44308438e24SVarun Wadekar .data 44408438e24SVarun Wadekar .align 3 44508438e24SVarun Wadekar 44608438e24SVarun Wadekar /* -------------------------------------------------- 44771cb26eaSVarun Wadekar * CPU Secure entry point - resume from suspend 44808438e24SVarun Wadekar * -------------------------------------------------- 44908438e24SVarun Wadekar */ 45071cb26eaSVarun Wadekartegra_sec_entry_point: 45108438e24SVarun Wadekar .quad 0 45208438e24SVarun Wadekar 45308438e24SVarun Wadekar /* -------------------------------------------------- 45408438e24SVarun Wadekar * NS world's cold boot entry point 45508438e24SVarun Wadekar * -------------------------------------------------- 45608438e24SVarun Wadekar */ 45708438e24SVarun Wadekarns_image_entrypoint: 45808438e24SVarun Wadekar .quad 0 45908438e24SVarun Wadekar 46008438e24SVarun Wadekar /* -------------------------------------------------- 46108438e24SVarun Wadekar * BL31's physical base address 46208438e24SVarun Wadekar * -------------------------------------------------- 46308438e24SVarun Wadekar */ 46408438e24SVarun Wadekartegra_bl31_phys_base: 46508438e24SVarun Wadekar .quad 0 466e1084216SVarun Wadekar 467e1084216SVarun Wadekar /* -------------------------------------------------- 468e1084216SVarun Wadekar * UART controller base for console init 469e1084216SVarun Wadekar * -------------------------------------------------- 470e1084216SVarun Wadekar */ 471e1084216SVarun Wadekartegra_console_base: 472e1084216SVarun Wadekar .quad 0 473018b8480SVarun Wadekar 474018b8480SVarun Wadekar /* -------------------------------------------------- 475018b8480SVarun Wadekar * Enable L2 ECC and Parity Protection 476018b8480SVarun Wadekar * -------------------------------------------------- 477018b8480SVarun Wadekar */ 478018b8480SVarun Wadekartegra_enable_l2_ecc_parity_prot: 479018b8480SVarun Wadekar .quad 0 480