108438e24SVarun Wadekar/* 208438e24SVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 408438e24SVarun Wadekar * Redistribution and use in source and binary forms, with or without 508438e24SVarun Wadekar * modification, are permitted provided that the following conditions are met: 608438e24SVarun Wadekar * 708438e24SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 808438e24SVarun Wadekar * list of conditions and the following disclaimer. 908438e24SVarun Wadekar * 1008438e24SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 1108438e24SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 1208438e24SVarun Wadekar * and/or other materials provided with the distribution. 1308438e24SVarun Wadekar * 1408438e24SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 1508438e24SVarun Wadekar * to endorse or promote products derived from this software without specific 1608438e24SVarun Wadekar * prior written permission. 1708438e24SVarun Wadekar * 1808438e24SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 1908438e24SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2008438e24SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2108438e24SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2208438e24SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2308438e24SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2408438e24SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2508438e24SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2608438e24SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2708438e24SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 2808438e24SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 2908438e24SVarun Wadekar */ 3008438e24SVarun Wadekar#include <arch.h> 3108438e24SVarun Wadekar#include <asm_macros.S> 3208438e24SVarun Wadekar#include <assert_macros.S> 3308438e24SVarun Wadekar#include <cpu_macros.S> 3408438e24SVarun Wadekar#include <cortex_a57.h> 3508438e24SVarun Wadekar#include <cortex_a53.h> 3608438e24SVarun Wadekar#include <tegra_def.h> 3708438e24SVarun Wadekar 380cd6138dSVarun Wadekar#define MIDR_PN_CORTEX_A57 0xD07 390cd6138dSVarun Wadekar 400cd6138dSVarun Wadekar/******************************************************************************* 410cd6138dSVarun Wadekar * Implementation defined ACTLR_EL3 bit definitions 420cd6138dSVarun Wadekar ******************************************************************************/ 430cd6138dSVarun Wadekar#define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 440cd6138dSVarun Wadekar#define ACTLR_EL3_L2ECTLR_BIT (1 << 5) 450cd6138dSVarun Wadekar#define ACTLR_EL3_L2CTLR_BIT (1 << 4) 460cd6138dSVarun Wadekar#define ACTLR_EL3_CPUECTLR_BIT (1 << 1) 470cd6138dSVarun Wadekar#define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 480cd6138dSVarun Wadekar#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ 490cd6138dSVarun Wadekar ACTLR_EL3_L2ECTLR_BIT | \ 500cd6138dSVarun Wadekar ACTLR_EL3_L2CTLR_BIT | \ 510cd6138dSVarun Wadekar ACTLR_EL3_CPUECTLR_BIT | \ 520cd6138dSVarun Wadekar ACTLR_EL3_CPUACTLR_BIT) 530cd6138dSVarun Wadekar 5408438e24SVarun Wadekar /* Global functions */ 5571cb26eaSVarun Wadekar .globl plat_is_my_cpu_primary 5671cb26eaSVarun Wadekar .globl plat_my_core_pos 5771cb26eaSVarun Wadekar .globl plat_get_my_entrypoint 5808438e24SVarun Wadekar .globl plat_secondary_cold_boot_setup 5908438e24SVarun Wadekar .globl platform_mem_init 6008438e24SVarun Wadekar .globl plat_crash_console_init 6108438e24SVarun Wadekar .globl plat_crash_console_putc 6208438e24SVarun Wadekar .globl tegra_secure_entrypoint 6308438e24SVarun Wadekar .globl plat_reset_handler 6408438e24SVarun Wadekar 6508438e24SVarun Wadekar /* Global variables */ 6671cb26eaSVarun Wadekar .globl tegra_sec_entry_point 6708438e24SVarun Wadekar .globl ns_image_entrypoint 6808438e24SVarun Wadekar .globl tegra_bl31_phys_base 69*e1084216SVarun Wadekar .globl tegra_console_base 7008438e24SVarun Wadekar 7108438e24SVarun Wadekar /* --------------------- 7208438e24SVarun Wadekar * Common CPU init code 7308438e24SVarun Wadekar * --------------------- 7408438e24SVarun Wadekar */ 7508438e24SVarun Wadekar.macro cpu_init_common 7608438e24SVarun Wadekar 770cd6138dSVarun Wadekar /* ------------------------------------------------ 780cd6138dSVarun Wadekar * We enable procesor retention and L2/CPUECTLR NS 790cd6138dSVarun Wadekar * access for A57 CPUs only. 800cd6138dSVarun Wadekar * ------------------------------------------------ 810cd6138dSVarun Wadekar */ 820cd6138dSVarun Wadekar mrs x0, midr_el1 830cd6138dSVarun Wadekar mov x1, #(MIDR_PN_MASK << MIDR_PN_SHIFT) 840cd6138dSVarun Wadekar and x0, x0, x1 850cd6138dSVarun Wadekar lsr x0, x0, #MIDR_PN_SHIFT 860cd6138dSVarun Wadekar cmp x0, #MIDR_PN_CORTEX_A57 870cd6138dSVarun Wadekar b.ne 1f 880cd6138dSVarun Wadekar 89b42192bcSVarun Wadekar /* --------------------------- 90b42192bcSVarun Wadekar * Enable processor retention 91b42192bcSVarun Wadekar * --------------------------- 92b42192bcSVarun Wadekar */ 93b42192bcSVarun Wadekar mrs x0, L2ECTLR_EL1 94b42192bcSVarun Wadekar mov x1, #RETENTION_ENTRY_TICKS_512 << L2ECTLR_RET_CTRL_SHIFT 95b42192bcSVarun Wadekar bic x0, x0, #L2ECTLR_RET_CTRL_MASK 96b42192bcSVarun Wadekar orr x0, x0, x1 97b42192bcSVarun Wadekar msr L2ECTLR_EL1, x0 98b42192bcSVarun Wadekar isb 99b42192bcSVarun Wadekar 100b42192bcSVarun Wadekar mrs x0, CPUECTLR_EL1 101b42192bcSVarun Wadekar mov x1, #RETENTION_ENTRY_TICKS_512 << CPUECTLR_CPU_RET_CTRL_SHIFT 102b42192bcSVarun Wadekar bic x0, x0, #CPUECTLR_CPU_RET_CTRL_MASK 103b42192bcSVarun Wadekar orr x0, x0, x1 104b42192bcSVarun Wadekar msr CPUECTLR_EL1, x0 105b42192bcSVarun Wadekar isb 106b42192bcSVarun Wadekar 10708438e24SVarun Wadekar /* ------------------------------------------------------- 10808438e24SVarun Wadekar * Enable L2 and CPU ECTLR RW access from non-secure world 10908438e24SVarun Wadekar * ------------------------------------------------------- 11008438e24SVarun Wadekar */ 11108438e24SVarun Wadekar mov x0, #ACTLR_EL3_ENABLE_ALL_ACCESS 11208438e24SVarun Wadekar msr actlr_el3, x0 11308438e24SVarun Wadekar msr actlr_el2, x0 11408438e24SVarun Wadekar isb 11508438e24SVarun Wadekar 11608438e24SVarun Wadekar /* -------------------------------- 11708438e24SVarun Wadekar * Enable the cycle count register 11808438e24SVarun Wadekar * -------------------------------- 11908438e24SVarun Wadekar */ 1200cd6138dSVarun Wadekar1: mrs x0, pmcr_el0 12108438e24SVarun Wadekar ubfx x0, x0, #11, #5 // read PMCR.N field 12208438e24SVarun Wadekar mov x1, #1 12308438e24SVarun Wadekar lsl x0, x1, x0 12408438e24SVarun Wadekar sub x0, x0, #1 // mask of event counters 12508438e24SVarun Wadekar orr x0, x0, #0x80000000 // disable overflow intrs 12608438e24SVarun Wadekar msr pmintenclr_el1, x0 12708438e24SVarun Wadekar msr pmuserenr_el0, x1 // enable user mode access 12808438e24SVarun Wadekar 12908438e24SVarun Wadekar /* ---------------------------------------------------------------- 13008438e24SVarun Wadekar * Allow non-privileged access to CNTVCT: Set CNTKCTL (Kernel Count 13108438e24SVarun Wadekar * register), bit 1 (EL0VCTEN) to enable access to CNTVCT/CNTFRQ 13208438e24SVarun Wadekar * registers from EL0. 13308438e24SVarun Wadekar * ---------------------------------------------------------------- 13408438e24SVarun Wadekar */ 13508438e24SVarun Wadekar mrs x0, cntkctl_el1 13608438e24SVarun Wadekar orr x0, x0, #EL0VCTEN_BIT 13708438e24SVarun Wadekar msr cntkctl_el1, x0 13808438e24SVarun Wadekar.endm 13908438e24SVarun Wadekar 14008438e24SVarun Wadekar /* ----------------------------------------------------- 14171cb26eaSVarun Wadekar * unsigned int plat_is_my_cpu_primary(void); 14208438e24SVarun Wadekar * 14308438e24SVarun Wadekar * This function checks if this is the Primary CPU 14408438e24SVarun Wadekar * ----------------------------------------------------- 14508438e24SVarun Wadekar */ 14671cb26eaSVarun Wadekarfunc plat_is_my_cpu_primary 14771cb26eaSVarun Wadekar mrs x0, mpidr_el1 14808438e24SVarun Wadekar and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 14908438e24SVarun Wadekar cmp x0, #TEGRA_PRIMARY_CPU 15008438e24SVarun Wadekar cset x0, eq 15108438e24SVarun Wadekar ret 15271cb26eaSVarun Wadekarendfunc plat_is_my_cpu_primary 15308438e24SVarun Wadekar 15408438e24SVarun Wadekar /* ----------------------------------------------------- 15571cb26eaSVarun Wadekar * unsigned int plat_my_core_pos(void); 15608438e24SVarun Wadekar * 15771cb26eaSVarun Wadekar * result: CorePos = CoreId + (ClusterId << 2) 15808438e24SVarun Wadekar * ----------------------------------------------------- 15908438e24SVarun Wadekar */ 16071cb26eaSVarun Wadekarfunc plat_my_core_pos 16171cb26eaSVarun Wadekar mrs x0, mpidr_el1 16271cb26eaSVarun Wadekar and x1, x0, #MPIDR_CPU_MASK 16371cb26eaSVarun Wadekar and x0, x0, #MPIDR_CLUSTER_MASK 16471cb26eaSVarun Wadekar add x0, x1, x0, LSR #6 16508438e24SVarun Wadekar ret 16671cb26eaSVarun Wadekarendfunc plat_my_core_pos 16771cb26eaSVarun Wadekar 16871cb26eaSVarun Wadekar /* ----------------------------------------------------- 16971cb26eaSVarun Wadekar * unsigned long plat_get_my_entrypoint (void); 17071cb26eaSVarun Wadekar * 17171cb26eaSVarun Wadekar * Main job of this routine is to distinguish between 17271cb26eaSVarun Wadekar * a cold and warm boot. If the tegra_sec_entry_point for 17371cb26eaSVarun Wadekar * this CPU is present, then it's a warm boot. 17471cb26eaSVarun Wadekar * 17571cb26eaSVarun Wadekar * ----------------------------------------------------- 17671cb26eaSVarun Wadekar */ 17771cb26eaSVarun Wadekarfunc plat_get_my_entrypoint 17871cb26eaSVarun Wadekar adr x1, tegra_sec_entry_point 17971cb26eaSVarun Wadekar ldr x0, [x1] 18071cb26eaSVarun Wadekar ret 18171cb26eaSVarun Wadekarendfunc plat_get_my_entrypoint 18208438e24SVarun Wadekar 18308438e24SVarun Wadekar /* ----------------------------------------------------- 184bde81dccSVarun Wadekar * int platform_get_core_pos(int mpidr); 185bde81dccSVarun Wadekar * 186bde81dccSVarun Wadekar * With this function: CorePos = (ClusterId * 4) + 187bde81dccSVarun Wadekar * CoreId 188bde81dccSVarun Wadekar * ----------------------------------------------------- 189bde81dccSVarun Wadekar */ 190bde81dccSVarun Wadekarfunc platform_get_core_pos 191bde81dccSVarun Wadekar and x1, x0, #MPIDR_CPU_MASK 192bde81dccSVarun Wadekar and x0, x0, #MPIDR_CLUSTER_MASK 193bde81dccSVarun Wadekar add x0, x1, x0, LSR #6 194bde81dccSVarun Wadekar ret 195bde81dccSVarun Wadekarendfunc platform_get_core_pos 196bde81dccSVarun Wadekar 197bde81dccSVarun Wadekar /* ----------------------------------------------------- 19808438e24SVarun Wadekar * void plat_secondary_cold_boot_setup (void); 19908438e24SVarun Wadekar * 20008438e24SVarun Wadekar * This function performs any platform specific actions 20108438e24SVarun Wadekar * needed for a secondary cpu after a cold reset. Right 20208438e24SVarun Wadekar * now this is a stub function. 20308438e24SVarun Wadekar * ----------------------------------------------------- 20408438e24SVarun Wadekar */ 20508438e24SVarun Wadekarfunc plat_secondary_cold_boot_setup 20608438e24SVarun Wadekar mov x0, #0 20708438e24SVarun Wadekar ret 20808438e24SVarun Wadekarendfunc plat_secondary_cold_boot_setup 20908438e24SVarun Wadekar 21008438e24SVarun Wadekar /* -------------------------------------------------------- 21108438e24SVarun Wadekar * void platform_mem_init (void); 21208438e24SVarun Wadekar * 21308438e24SVarun Wadekar * Any memory init, relocation to be done before the 21408438e24SVarun Wadekar * platform boots. Called very early in the boot process. 21508438e24SVarun Wadekar * -------------------------------------------------------- 21608438e24SVarun Wadekar */ 21708438e24SVarun Wadekarfunc platform_mem_init 21808438e24SVarun Wadekar mov x0, #0 21908438e24SVarun Wadekar ret 22008438e24SVarun Wadekarendfunc platform_mem_init 22108438e24SVarun Wadekar 22208438e24SVarun Wadekar /* --------------------------------------------- 22308438e24SVarun Wadekar * int plat_crash_console_init(void) 22408438e24SVarun Wadekar * Function to initialize the crash console 22508438e24SVarun Wadekar * without a C Runtime to print crash report. 2269400b40eSJuan Castillo * Clobber list : x0 - x4 22708438e24SVarun Wadekar * --------------------------------------------- 22808438e24SVarun Wadekar */ 22908438e24SVarun Wadekarfunc plat_crash_console_init 230*e1084216SVarun Wadekar adr x0, tegra_console_base 231*e1084216SVarun Wadekar ldr x0, [x0] 23208438e24SVarun Wadekar mov_imm x1, TEGRA_BOOT_UART_CLK_IN_HZ 23308438e24SVarun Wadekar mov_imm x2, TEGRA_CONSOLE_BAUDRATE 23408438e24SVarun Wadekar b console_core_init 23508438e24SVarun Wadekarendfunc plat_crash_console_init 23608438e24SVarun Wadekar 23708438e24SVarun Wadekar /* --------------------------------------------- 23808438e24SVarun Wadekar * int plat_crash_console_putc(void) 23908438e24SVarun Wadekar * Function to print a character on the crash 24008438e24SVarun Wadekar * console without a C Runtime. 24108438e24SVarun Wadekar * Clobber list : x1, x2 24208438e24SVarun Wadekar * --------------------------------------------- 24308438e24SVarun Wadekar */ 24408438e24SVarun Wadekarfunc plat_crash_console_putc 245*e1084216SVarun Wadekar adr x1, tegra_console_base 246*e1084216SVarun Wadekar ldr x1, [x1] 24708438e24SVarun Wadekar b console_core_putc 24808438e24SVarun Wadekarendfunc plat_crash_console_putc 24908438e24SVarun Wadekar 25008438e24SVarun Wadekar /* --------------------------------------------------- 25108438e24SVarun Wadekar * Function to handle a platform reset and store 25208438e24SVarun Wadekar * input parameters passed by BL2. 25308438e24SVarun Wadekar * --------------------------------------------------- 25408438e24SVarun Wadekar */ 25508438e24SVarun Wadekarfunc plat_reset_handler 25608438e24SVarun Wadekar 25708438e24SVarun Wadekar /* ----------------------------------- 25808438e24SVarun Wadekar * derive and save the phys_base addr 25908438e24SVarun Wadekar * ----------------------------------- 26008438e24SVarun Wadekar */ 26108438e24SVarun Wadekar adr x17, tegra_bl31_phys_base 26208438e24SVarun Wadekar ldr x18, [x17] 26308438e24SVarun Wadekar cbnz x18, 1f 26408438e24SVarun Wadekar adr x18, bl31_entrypoint 26508438e24SVarun Wadekar str x18, [x17] 26608438e24SVarun Wadekar 26708438e24SVarun Wadekar1: cpu_init_common 26808438e24SVarun Wadekar 26908438e24SVarun Wadekar ret 27008438e24SVarun Wadekarendfunc plat_reset_handler 27108438e24SVarun Wadekar 27208438e24SVarun Wadekar /* ---------------------------------------- 27308438e24SVarun Wadekar * Secure entrypoint function for CPU boot 27408438e24SVarun Wadekar * ---------------------------------------- 27508438e24SVarun Wadekar */ 27608438e24SVarun Wadekar .align 6 27708438e24SVarun Wadekarfunc tegra_secure_entrypoint 27808438e24SVarun Wadekar 27908438e24SVarun Wadekar#if ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT 28008438e24SVarun Wadekar 28108438e24SVarun Wadekar /* ------------------------------------------------------- 28208438e24SVarun Wadekar * Invalidate BTB along with I$ to remove any stale 28308438e24SVarun Wadekar * entries from the branch predictor array. 28408438e24SVarun Wadekar * ------------------------------------------------------- 28508438e24SVarun Wadekar */ 28608438e24SVarun Wadekar mrs x0, CPUACTLR_EL1 28708438e24SVarun Wadekar orr x0, x0, #1 28808438e24SVarun Wadekar msr CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */ 28908438e24SVarun Wadekar dsb sy 29008438e24SVarun Wadekar isb 29108438e24SVarun Wadekar ic iallu /* actual invalidate */ 29208438e24SVarun Wadekar dsb sy 29308438e24SVarun Wadekar isb 29408438e24SVarun Wadekar 29508438e24SVarun Wadekar mrs x0, CPUACTLR_EL1 29608438e24SVarun Wadekar bic x0, x0, #1 29708438e24SVarun Wadekar msr CPUACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */ 29808438e24SVarun Wadekar dsb sy 29908438e24SVarun Wadekar isb 30008438e24SVarun Wadekar 30108438e24SVarun Wadekar .rept 7 30208438e24SVarun Wadekar nop /* wait */ 30308438e24SVarun Wadekar .endr 30408438e24SVarun Wadekar 30508438e24SVarun Wadekar /* ----------------------------------------------- 30608438e24SVarun Wadekar * Extract OSLK bit and check if it is '1'. This 30708438e24SVarun Wadekar * bit remains '0' for A53 on warm-resets. If '1', 30808438e24SVarun Wadekar * turn off regional clock gating and request warm 30908438e24SVarun Wadekar * reset. 31008438e24SVarun Wadekar * ----------------------------------------------- 31108438e24SVarun Wadekar */ 31208438e24SVarun Wadekar mrs x0, oslsr_el1 31308438e24SVarun Wadekar and x0, x0, #2 31408438e24SVarun Wadekar mrs x1, mpidr_el1 31508438e24SVarun Wadekar bics xzr, x0, x1, lsr #7 /* 0 = slow cluster or warm reset */ 31608438e24SVarun Wadekar b.eq restore_oslock 31708438e24SVarun Wadekar mov x0, xzr 31808438e24SVarun Wadekar msr oslar_el1, x0 /* os lock stays 0 across warm reset */ 31908438e24SVarun Wadekar mov x3, #3 32008438e24SVarun Wadekar movz x4, #0x8000, lsl #48 32108438e24SVarun Wadekar msr CPUACTLR_EL1, x4 /* turn off RCG */ 32208438e24SVarun Wadekar isb 32308438e24SVarun Wadekar msr rmr_el3, x3 /* request warm reset */ 32408438e24SVarun Wadekar isb 32508438e24SVarun Wadekar dsb sy 32608438e24SVarun Wadekar1: wfi 32708438e24SVarun Wadekar b 1b 32808438e24SVarun Wadekar 32908438e24SVarun Wadekar /* -------------------------------------------------- 33008438e24SVarun Wadekar * These nops are here so that speculative execution 33108438e24SVarun Wadekar * won't harm us before we are done with warm reset. 33208438e24SVarun Wadekar * -------------------------------------------------- 33308438e24SVarun Wadekar */ 33408438e24SVarun Wadekar .rept 65 33508438e24SVarun Wadekar nop 33608438e24SVarun Wadekar .endr 33708438e24SVarun Wadekar 33808438e24SVarun Wadekar /* -------------------------------------------------- 33908438e24SVarun Wadekar * Do not insert instructions here 34008438e24SVarun Wadekar * -------------------------------------------------- 34108438e24SVarun Wadekar */ 34208438e24SVarun Wadekar#endif 34308438e24SVarun Wadekar 34408438e24SVarun Wadekar /* -------------------------------------------------- 34508438e24SVarun Wadekar * Restore OS Lock bit 34608438e24SVarun Wadekar * -------------------------------------------------- 34708438e24SVarun Wadekar */ 34808438e24SVarun Wadekarrestore_oslock: 34908438e24SVarun Wadekar mov x0, #1 35008438e24SVarun Wadekar msr oslar_el1, x0 35108438e24SVarun Wadekar 35208438e24SVarun Wadekar cpu_init_common 35308438e24SVarun Wadekar 35408438e24SVarun Wadekar /* --------------------------------------------------------------------- 35508438e24SVarun Wadekar * The initial state of the Architectural feature trap register 35608438e24SVarun Wadekar * (CPTR_EL3) is unknown and it must be set to a known state. All 35708438e24SVarun Wadekar * feature traps are disabled. Some bits in this register are marked as 35808438e24SVarun Wadekar * Reserved and should not be modified. 35908438e24SVarun Wadekar * 36008438e24SVarun Wadekar * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1 36108438e24SVarun Wadekar * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2. 36208438e24SVarun Wadekar * CPTR_EL3.TTA: This causes access to the Trace functionality to trap 36308438e24SVarun Wadekar * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register 36408438e24SVarun Wadekar * access to trace functionality is not supported, this bit is RES0. 36508438e24SVarun Wadekar * CPTR_EL3.TFP: This causes instructions that access the registers 36608438e24SVarun Wadekar * associated with Floating Point and Advanced SIMD execution to trap 36708438e24SVarun Wadekar * to EL3 when executed from any exception level, unless trapped to EL1 36808438e24SVarun Wadekar * or EL2. 36908438e24SVarun Wadekar * --------------------------------------------------------------------- 37008438e24SVarun Wadekar */ 37108438e24SVarun Wadekar mrs x1, cptr_el3 37208438e24SVarun Wadekar bic w1, w1, #TCPAC_BIT 37308438e24SVarun Wadekar bic w1, w1, #TTA_BIT 37408438e24SVarun Wadekar bic w1, w1, #TFP_BIT 37508438e24SVarun Wadekar msr cptr_el3, x1 37608438e24SVarun Wadekar 37708438e24SVarun Wadekar /* -------------------------------------------------- 37808438e24SVarun Wadekar * Get secure world's entry point and jump to it 37908438e24SVarun Wadekar * -------------------------------------------------- 38008438e24SVarun Wadekar */ 38171cb26eaSVarun Wadekar bl plat_get_my_entrypoint 38208438e24SVarun Wadekar br x0 38308438e24SVarun Wadekarendfunc tegra_secure_entrypoint 38408438e24SVarun Wadekar 38508438e24SVarun Wadekar .data 38608438e24SVarun Wadekar .align 3 38708438e24SVarun Wadekar 38808438e24SVarun Wadekar /* -------------------------------------------------- 38971cb26eaSVarun Wadekar * CPU Secure entry point - resume from suspend 39008438e24SVarun Wadekar * -------------------------------------------------- 39108438e24SVarun Wadekar */ 39271cb26eaSVarun Wadekartegra_sec_entry_point: 39308438e24SVarun Wadekar .quad 0 39408438e24SVarun Wadekar 39508438e24SVarun Wadekar /* -------------------------------------------------- 39608438e24SVarun Wadekar * NS world's cold boot entry point 39708438e24SVarun Wadekar * -------------------------------------------------- 39808438e24SVarun Wadekar */ 39908438e24SVarun Wadekarns_image_entrypoint: 40008438e24SVarun Wadekar .quad 0 40108438e24SVarun Wadekar 40208438e24SVarun Wadekar /* -------------------------------------------------- 40308438e24SVarun Wadekar * BL31's physical base address 40408438e24SVarun Wadekar * -------------------------------------------------- 40508438e24SVarun Wadekar */ 40608438e24SVarun Wadekartegra_bl31_phys_base: 40708438e24SVarun Wadekar .quad 0 408*e1084216SVarun Wadekar 409*e1084216SVarun Wadekar /* -------------------------------------------------- 410*e1084216SVarun Wadekar * UART controller base for console init 411*e1084216SVarun Wadekar * -------------------------------------------------- 412*e1084216SVarun Wadekar */ 413*e1084216SVarun Wadekartegra_console_base: 414*e1084216SVarun Wadekar .quad 0 415