108438e24SVarun Wadekar/* 29c675b37SAntonio Nino Diaz * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 508438e24SVarun Wadekar */ 608438e24SVarun Wadekar#include <arch.h> 708438e24SVarun Wadekar#include <asm_macros.S> 808438e24SVarun Wadekar#include <assert_macros.S> 908438e24SVarun Wadekar#include <cpu_macros.S> 1008438e24SVarun Wadekar#include <cortex_a53.h> 11ee1ebbd1SIsla Mitchell#include <cortex_a57.h> 1211bd24beSVarun Wadekar#include <platform_def.h> 1308438e24SVarun Wadekar#include <tegra_def.h> 14*c195fec6SHarvey Hsieh#include <tegra_platform.h> 1508438e24SVarun Wadekar 160cd6138dSVarun Wadekar#define MIDR_PN_CORTEX_A57 0xD07 170cd6138dSVarun Wadekar 180cd6138dSVarun Wadekar/******************************************************************************* 190cd6138dSVarun Wadekar * Implementation defined ACTLR_EL3 bit definitions 200cd6138dSVarun Wadekar ******************************************************************************/ 210cd6138dSVarun Wadekar#define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 220cd6138dSVarun Wadekar#define ACTLR_EL3_L2ECTLR_BIT (1 << 5) 230cd6138dSVarun Wadekar#define ACTLR_EL3_L2CTLR_BIT (1 << 4) 240cd6138dSVarun Wadekar#define ACTLR_EL3_CPUECTLR_BIT (1 << 1) 250cd6138dSVarun Wadekar#define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 260cd6138dSVarun Wadekar#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ 270cd6138dSVarun Wadekar ACTLR_EL3_L2ECTLR_BIT | \ 280cd6138dSVarun Wadekar ACTLR_EL3_L2CTLR_BIT | \ 290cd6138dSVarun Wadekar ACTLR_EL3_CPUECTLR_BIT | \ 300cd6138dSVarun Wadekar ACTLR_EL3_CPUACTLR_BIT) 310cd6138dSVarun Wadekar 3208438e24SVarun Wadekar /* Global functions */ 3371cb26eaSVarun Wadekar .globl plat_is_my_cpu_primary 3471cb26eaSVarun Wadekar .globl plat_my_core_pos 3571cb26eaSVarun Wadekar .globl plat_get_my_entrypoint 3608438e24SVarun Wadekar .globl plat_secondary_cold_boot_setup 3708438e24SVarun Wadekar .globl platform_mem_init 3808438e24SVarun Wadekar .globl plat_crash_console_init 3908438e24SVarun Wadekar .globl plat_crash_console_putc 409c675b37SAntonio Nino Diaz .globl plat_crash_console_flush 4108438e24SVarun Wadekar .globl tegra_secure_entrypoint 4208438e24SVarun Wadekar .globl plat_reset_handler 4308438e24SVarun Wadekar 4408438e24SVarun Wadekar /* Global variables */ 4571cb26eaSVarun Wadekar .globl tegra_sec_entry_point 4608438e24SVarun Wadekar .globl ns_image_entrypoint 4708438e24SVarun Wadekar .globl tegra_bl31_phys_base 48e1084216SVarun Wadekar .globl tegra_console_base 4908438e24SVarun Wadekar 5008438e24SVarun Wadekar /* --------------------- 5108438e24SVarun Wadekar * Common CPU init code 5208438e24SVarun Wadekar * --------------------- 5308438e24SVarun Wadekar */ 5408438e24SVarun Wadekar.macro cpu_init_common 5508438e24SVarun Wadekar 560cd6138dSVarun Wadekar /* ------------------------------------------------ 57018b8480SVarun Wadekar * We enable procesor retention, L2/CPUECTLR NS 58018b8480SVarun Wadekar * access and ECC/Parity protection for A57 CPUs 590cd6138dSVarun Wadekar * ------------------------------------------------ 600cd6138dSVarun Wadekar */ 610cd6138dSVarun Wadekar mrs x0, midr_el1 620cd6138dSVarun Wadekar mov x1, #(MIDR_PN_MASK << MIDR_PN_SHIFT) 630cd6138dSVarun Wadekar and x0, x0, x1 640cd6138dSVarun Wadekar lsr x0, x0, #MIDR_PN_SHIFT 650cd6138dSVarun Wadekar cmp x0, #MIDR_PN_CORTEX_A57 660cd6138dSVarun Wadekar b.ne 1f 670cd6138dSVarun Wadekar 68b42192bcSVarun Wadekar /* --------------------------- 69b42192bcSVarun Wadekar * Enable processor retention 70b42192bcSVarun Wadekar * --------------------------- 71b42192bcSVarun Wadekar */ 72fb7d32e5SVarun Wadekar mrs x0, CORTEX_A57_L2ECTLR_EL1 73fb7d32e5SVarun Wadekar mov x1, #RETENTION_ENTRY_TICKS_512 74fb7d32e5SVarun Wadekar bic x0, x0, #CORTEX_A57_L2ECTLR_RET_CTRL_MASK 75b42192bcSVarun Wadekar orr x0, x0, x1 76fb7d32e5SVarun Wadekar msr CORTEX_A57_L2ECTLR_EL1, x0 77b42192bcSVarun Wadekar isb 78b42192bcSVarun Wadekar 79fb7d32e5SVarun Wadekar mrs x0, CORTEX_A57_ECTLR_EL1 80fb7d32e5SVarun Wadekar mov x1, #RETENTION_ENTRY_TICKS_512 81fb7d32e5SVarun Wadekar bic x0, x0, #CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK 82b42192bcSVarun Wadekar orr x0, x0, x1 83fb7d32e5SVarun Wadekar msr CORTEX_A57_ECTLR_EL1, x0 84b42192bcSVarun Wadekar isb 85b42192bcSVarun Wadekar 8608438e24SVarun Wadekar /* ------------------------------------------------------- 8708438e24SVarun Wadekar * Enable L2 and CPU ECTLR RW access from non-secure world 8808438e24SVarun Wadekar * ------------------------------------------------------- 8908438e24SVarun Wadekar */ 9008438e24SVarun Wadekar mov x0, #ACTLR_EL3_ENABLE_ALL_ACCESS 9108438e24SVarun Wadekar msr actlr_el3, x0 9208438e24SVarun Wadekar msr actlr_el2, x0 9308438e24SVarun Wadekar isb 9408438e24SVarun Wadekar 9508438e24SVarun Wadekar /* -------------------------------- 9608438e24SVarun Wadekar * Enable the cycle count register 9708438e24SVarun Wadekar * -------------------------------- 9808438e24SVarun Wadekar */ 990cd6138dSVarun Wadekar1: mrs x0, pmcr_el0 10008438e24SVarun Wadekar ubfx x0, x0, #11, #5 // read PMCR.N field 10108438e24SVarun Wadekar mov x1, #1 10208438e24SVarun Wadekar lsl x0, x1, x0 10308438e24SVarun Wadekar sub x0, x0, #1 // mask of event counters 10408438e24SVarun Wadekar orr x0, x0, #0x80000000 // disable overflow intrs 10508438e24SVarun Wadekar msr pmintenclr_el1, x0 10608438e24SVarun Wadekar msr pmuserenr_el0, x1 // enable user mode access 10708438e24SVarun Wadekar 10808438e24SVarun Wadekar /* ---------------------------------------------------------------- 10908438e24SVarun Wadekar * Allow non-privileged access to CNTVCT: Set CNTKCTL (Kernel Count 11008438e24SVarun Wadekar * register), bit 1 (EL0VCTEN) to enable access to CNTVCT/CNTFRQ 11108438e24SVarun Wadekar * registers from EL0. 11208438e24SVarun Wadekar * ---------------------------------------------------------------- 11308438e24SVarun Wadekar */ 11408438e24SVarun Wadekar mrs x0, cntkctl_el1 11508438e24SVarun Wadekar orr x0, x0, #EL0VCTEN_BIT 11608438e24SVarun Wadekar msr cntkctl_el1, x0 11708438e24SVarun Wadekar.endm 11808438e24SVarun Wadekar 11908438e24SVarun Wadekar /* ----------------------------------------------------- 12071cb26eaSVarun Wadekar * unsigned int plat_is_my_cpu_primary(void); 12108438e24SVarun Wadekar * 12208438e24SVarun Wadekar * This function checks if this is the Primary CPU 12308438e24SVarun Wadekar * ----------------------------------------------------- 12408438e24SVarun Wadekar */ 12571cb26eaSVarun Wadekarfunc plat_is_my_cpu_primary 12671cb26eaSVarun Wadekar mrs x0, mpidr_el1 12708438e24SVarun Wadekar and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 12808438e24SVarun Wadekar cmp x0, #TEGRA_PRIMARY_CPU 12908438e24SVarun Wadekar cset x0, eq 13008438e24SVarun Wadekar ret 13171cb26eaSVarun Wadekarendfunc plat_is_my_cpu_primary 13208438e24SVarun Wadekar 13308438e24SVarun Wadekar /* ----------------------------------------------------- 13471cb26eaSVarun Wadekar * unsigned int plat_my_core_pos(void); 13508438e24SVarun Wadekar * 13671cb26eaSVarun Wadekar * result: CorePos = CoreId + (ClusterId << 2) 13708438e24SVarun Wadekar * ----------------------------------------------------- 13808438e24SVarun Wadekar */ 13971cb26eaSVarun Wadekarfunc plat_my_core_pos 14071cb26eaSVarun Wadekar mrs x0, mpidr_el1 14171cb26eaSVarun Wadekar and x1, x0, #MPIDR_CPU_MASK 14271cb26eaSVarun Wadekar and x0, x0, #MPIDR_CLUSTER_MASK 14371cb26eaSVarun Wadekar add x0, x1, x0, LSR #6 14408438e24SVarun Wadekar ret 14571cb26eaSVarun Wadekarendfunc plat_my_core_pos 14671cb26eaSVarun Wadekar 14771cb26eaSVarun Wadekar /* ----------------------------------------------------- 14871cb26eaSVarun Wadekar * unsigned long plat_get_my_entrypoint (void); 14971cb26eaSVarun Wadekar * 15071cb26eaSVarun Wadekar * Main job of this routine is to distinguish between 15171cb26eaSVarun Wadekar * a cold and warm boot. If the tegra_sec_entry_point for 15271cb26eaSVarun Wadekar * this CPU is present, then it's a warm boot. 15371cb26eaSVarun Wadekar * 15471cb26eaSVarun Wadekar * ----------------------------------------------------- 15571cb26eaSVarun Wadekar */ 15671cb26eaSVarun Wadekarfunc plat_get_my_entrypoint 15771cb26eaSVarun Wadekar adr x1, tegra_sec_entry_point 15871cb26eaSVarun Wadekar ldr x0, [x1] 15971cb26eaSVarun Wadekar ret 16071cb26eaSVarun Wadekarendfunc plat_get_my_entrypoint 16108438e24SVarun Wadekar 16208438e24SVarun Wadekar /* ----------------------------------------------------- 163bde81dccSVarun Wadekar * int platform_get_core_pos(int mpidr); 164bde81dccSVarun Wadekar * 165bde81dccSVarun Wadekar * With this function: CorePos = (ClusterId * 4) + 166bde81dccSVarun Wadekar * CoreId 167bde81dccSVarun Wadekar * ----------------------------------------------------- 168bde81dccSVarun Wadekar */ 169bde81dccSVarun Wadekarfunc platform_get_core_pos 170bde81dccSVarun Wadekar and x1, x0, #MPIDR_CPU_MASK 171bde81dccSVarun Wadekar and x0, x0, #MPIDR_CLUSTER_MASK 172bde81dccSVarun Wadekar add x0, x1, x0, LSR #6 173bde81dccSVarun Wadekar ret 174bde81dccSVarun Wadekarendfunc platform_get_core_pos 175bde81dccSVarun Wadekar 176bde81dccSVarun Wadekar /* ----------------------------------------------------- 17708438e24SVarun Wadekar * void plat_secondary_cold_boot_setup (void); 17808438e24SVarun Wadekar * 17908438e24SVarun Wadekar * This function performs any platform specific actions 18008438e24SVarun Wadekar * needed for a secondary cpu after a cold reset. Right 18108438e24SVarun Wadekar * now this is a stub function. 18208438e24SVarun Wadekar * ----------------------------------------------------- 18308438e24SVarun Wadekar */ 18408438e24SVarun Wadekarfunc plat_secondary_cold_boot_setup 18508438e24SVarun Wadekar mov x0, #0 18608438e24SVarun Wadekar ret 18708438e24SVarun Wadekarendfunc plat_secondary_cold_boot_setup 18808438e24SVarun Wadekar 18908438e24SVarun Wadekar /* -------------------------------------------------------- 19008438e24SVarun Wadekar * void platform_mem_init (void); 19108438e24SVarun Wadekar * 19208438e24SVarun Wadekar * Any memory init, relocation to be done before the 19308438e24SVarun Wadekar * platform boots. Called very early in the boot process. 19408438e24SVarun Wadekar * -------------------------------------------------------- 19508438e24SVarun Wadekar */ 19608438e24SVarun Wadekarfunc platform_mem_init 19708438e24SVarun Wadekar mov x0, #0 19808438e24SVarun Wadekar ret 19908438e24SVarun Wadekarendfunc platform_mem_init 20008438e24SVarun Wadekar 20108438e24SVarun Wadekar /* --------------------------------------------- 20208438e24SVarun Wadekar * int plat_crash_console_init(void) 20308438e24SVarun Wadekar * Function to initialize the crash console 20408438e24SVarun Wadekar * without a C Runtime to print crash report. 2059400b40eSJuan Castillo * Clobber list : x0 - x4 20608438e24SVarun Wadekar * --------------------------------------------- 20708438e24SVarun Wadekar */ 20808438e24SVarun Wadekarfunc plat_crash_console_init 209e87dac6bSVarun Wadekar mov x0, #0 210e87dac6bSVarun Wadekar adr x1, tegra_console_base 211e87dac6bSVarun Wadekar ldr x1, [x1] 212e87dac6bSVarun Wadekar cbz x1, 1f 213e87dac6bSVarun Wadekar mov w0, #1 214e87dac6bSVarun Wadekar1: ret 21508438e24SVarun Wadekarendfunc plat_crash_console_init 21608438e24SVarun Wadekar 21708438e24SVarun Wadekar /* --------------------------------------------- 21808438e24SVarun Wadekar * int plat_crash_console_putc(void) 21908438e24SVarun Wadekar * Function to print a character on the crash 22008438e24SVarun Wadekar * console without a C Runtime. 22108438e24SVarun Wadekar * Clobber list : x1, x2 22208438e24SVarun Wadekar * --------------------------------------------- 22308438e24SVarun Wadekar */ 22408438e24SVarun Wadekarfunc plat_crash_console_putc 225e1084216SVarun Wadekar adr x1, tegra_console_base 226e1084216SVarun Wadekar ldr x1, [x1] 22708438e24SVarun Wadekar b console_core_putc 22808438e24SVarun Wadekarendfunc plat_crash_console_putc 22908438e24SVarun Wadekar 2309c675b37SAntonio Nino Diaz /* --------------------------------------------- 2319c675b37SAntonio Nino Diaz * int plat_crash_console_flush() 2329c675b37SAntonio Nino Diaz * Function to force a write of all buffered 2339c675b37SAntonio Nino Diaz * data that hasn't been output. 2349c675b37SAntonio Nino Diaz * Out : return -1 on error else return 0. 2359c675b37SAntonio Nino Diaz * Clobber list : x0, x1 2369c675b37SAntonio Nino Diaz * --------------------------------------------- 2379c675b37SAntonio Nino Diaz */ 2389c675b37SAntonio Nino Diazfunc plat_crash_console_flush 2399c675b37SAntonio Nino Diaz adr x0, tegra_console_base 2409c675b37SAntonio Nino Diaz ldr x0, [x0] 2419c675b37SAntonio Nino Diaz b console_core_flush 2429c675b37SAntonio Nino Diazendfunc plat_crash_console_flush 2439c675b37SAntonio Nino Diaz 24408438e24SVarun Wadekar /* --------------------------------------------------- 24508438e24SVarun Wadekar * Function to handle a platform reset and store 24608438e24SVarun Wadekar * input parameters passed by BL2. 24708438e24SVarun Wadekar * --------------------------------------------------- 24808438e24SVarun Wadekar */ 24908438e24SVarun Wadekarfunc plat_reset_handler 25008438e24SVarun Wadekar 251939dcf25SVarun Wadekar /* ---------------------------------------------------- 252939dcf25SVarun Wadekar * Verify if we are running from BL31_BASE address 253939dcf25SVarun Wadekar * ---------------------------------------------------- 254939dcf25SVarun Wadekar */ 255939dcf25SVarun Wadekar adr x18, bl31_entrypoint 256939dcf25SVarun Wadekar mov x17, #BL31_BASE 257939dcf25SVarun Wadekar cmp x18, x17 258939dcf25SVarun Wadekar b.eq 1f 259939dcf25SVarun Wadekar 260939dcf25SVarun Wadekar /* ---------------------------------------------------- 261939dcf25SVarun Wadekar * Copy the entire BL31 code to BL31_BASE if we are not 262939dcf25SVarun Wadekar * running from it already 263939dcf25SVarun Wadekar * ---------------------------------------------------- 264939dcf25SVarun Wadekar */ 265939dcf25SVarun Wadekar mov x0, x17 266939dcf25SVarun Wadekar mov x1, x18 267939dcf25SVarun Wadekar mov x2, #BL31_SIZE 268939dcf25SVarun Wadekar_loop16: 269939dcf25SVarun Wadekar cmp x2, #16 270768baf6eSDouglas Raillard b.lo _loop1 271939dcf25SVarun Wadekar ldp x3, x4, [x1], #16 272939dcf25SVarun Wadekar stp x3, x4, [x0], #16 273939dcf25SVarun Wadekar sub x2, x2, #16 274939dcf25SVarun Wadekar b _loop16 275939dcf25SVarun Wadekar /* copy byte per byte */ 276939dcf25SVarun Wadekar_loop1: 277939dcf25SVarun Wadekar cbz x2, _end 278939dcf25SVarun Wadekar ldrb w3, [x1], #1 279939dcf25SVarun Wadekar strb w3, [x0], #1 280939dcf25SVarun Wadekar subs x2, x2, #1 281939dcf25SVarun Wadekar b.ne _loop1 282939dcf25SVarun Wadekar 283939dcf25SVarun Wadekar /* ---------------------------------------------------- 284939dcf25SVarun Wadekar * Jump to BL31_BASE and start execution again 285939dcf25SVarun Wadekar * ---------------------------------------------------- 286939dcf25SVarun Wadekar */ 287939dcf25SVarun Wadekar_end: mov x0, x20 288939dcf25SVarun Wadekar mov x1, x21 289939dcf25SVarun Wadekar br x17 290939dcf25SVarun Wadekar1: 291939dcf25SVarun Wadekar 29208438e24SVarun Wadekar /* ----------------------------------- 29308438e24SVarun Wadekar * derive and save the phys_base addr 29408438e24SVarun Wadekar * ----------------------------------- 29508438e24SVarun Wadekar */ 29608438e24SVarun Wadekar adr x17, tegra_bl31_phys_base 29708438e24SVarun Wadekar ldr x18, [x17] 29808438e24SVarun Wadekar cbnz x18, 1f 29908438e24SVarun Wadekar adr x18, bl31_entrypoint 30008438e24SVarun Wadekar str x18, [x17] 30108438e24SVarun Wadekar 30208438e24SVarun Wadekar1: cpu_init_common 30308438e24SVarun Wadekar 30408438e24SVarun Wadekar ret 30508438e24SVarun Wadekarendfunc plat_reset_handler 30608438e24SVarun Wadekar 30708438e24SVarun Wadekar /* ---------------------------------------- 30808438e24SVarun Wadekar * Secure entrypoint function for CPU boot 30908438e24SVarun Wadekar * ---------------------------------------- 31008438e24SVarun Wadekar */ 31164726e6dSJulius Wernerfunc tegra_secure_entrypoint _align=6 31208438e24SVarun Wadekar 31308438e24SVarun Wadekar#if ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT 31408438e24SVarun Wadekar 315*c195fec6SHarvey Hsieh /* -------------------------------------------------------- 316*c195fec6SHarvey Hsieh * Skip the invalidate BTB workaround for Tegra210B01 SKUs. 317*c195fec6SHarvey Hsieh * -------------------------------------------------------- 318*c195fec6SHarvey Hsieh */ 319*c195fec6SHarvey Hsieh mov x0, #TEGRA_MISC_BASE 320*c195fec6SHarvey Hsieh add x0, x0, #HARDWARE_REVISION_OFFSET 321*c195fec6SHarvey Hsieh ldr w1, [x0] 322*c195fec6SHarvey Hsieh lsr w1, w1, #CHIP_ID_SHIFT 323*c195fec6SHarvey Hsieh and w1, w1, #CHIP_ID_MASK 324*c195fec6SHarvey Hsieh cmp w1, #TEGRA_CHIPID_TEGRA21 /* T210? */ 325*c195fec6SHarvey Hsieh b.ne 2f 326*c195fec6SHarvey Hsieh ldr w1, [x0] 327*c195fec6SHarvey Hsieh lsr w1, w1, #MAJOR_VERSION_SHIFT 328*c195fec6SHarvey Hsieh and w1, w1, #MAJOR_VERSION_MASK 329*c195fec6SHarvey Hsieh cmp w1, #0x02 /* T210 B01? */ 330*c195fec6SHarvey Hsieh b.eq 2f 331*c195fec6SHarvey Hsieh 33208438e24SVarun Wadekar /* ------------------------------------------------------- 33308438e24SVarun Wadekar * Invalidate BTB along with I$ to remove any stale 33408438e24SVarun Wadekar * entries from the branch predictor array. 33508438e24SVarun Wadekar * ------------------------------------------------------- 33608438e24SVarun Wadekar */ 337d0e1094eSEleanor Bonnici mrs x0, CORTEX_A57_CPUACTLR_EL1 33808438e24SVarun Wadekar orr x0, x0, #1 339d0e1094eSEleanor Bonnici msr CORTEX_A57_CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */ 34008438e24SVarun Wadekar dsb sy 34108438e24SVarun Wadekar isb 34208438e24SVarun Wadekar ic iallu /* actual invalidate */ 34308438e24SVarun Wadekar dsb sy 34408438e24SVarun Wadekar isb 34508438e24SVarun Wadekar 346d0e1094eSEleanor Bonnici mrs x0, CORTEX_A57_CPUACTLR_EL1 34708438e24SVarun Wadekar bic x0, x0, #1 348d0e1094eSEleanor Bonnici msr CORTEX_A57_CPUACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */ 34908438e24SVarun Wadekar dsb sy 35008438e24SVarun Wadekar isb 35108438e24SVarun Wadekar 35208438e24SVarun Wadekar .rept 7 35308438e24SVarun Wadekar nop /* wait */ 35408438e24SVarun Wadekar .endr 35508438e24SVarun Wadekar 35608438e24SVarun Wadekar /* ----------------------------------------------- 35708438e24SVarun Wadekar * Extract OSLK bit and check if it is '1'. This 35808438e24SVarun Wadekar * bit remains '0' for A53 on warm-resets. If '1', 35908438e24SVarun Wadekar * turn off regional clock gating and request warm 36008438e24SVarun Wadekar * reset. 36108438e24SVarun Wadekar * ----------------------------------------------- 36208438e24SVarun Wadekar */ 36308438e24SVarun Wadekar mrs x0, oslsr_el1 36408438e24SVarun Wadekar and x0, x0, #2 36508438e24SVarun Wadekar mrs x1, mpidr_el1 36608438e24SVarun Wadekar bics xzr, x0, x1, lsr #7 /* 0 = slow cluster or warm reset */ 36708438e24SVarun Wadekar b.eq restore_oslock 36808438e24SVarun Wadekar mov x0, xzr 36908438e24SVarun Wadekar msr oslar_el1, x0 /* os lock stays 0 across warm reset */ 37008438e24SVarun Wadekar mov x3, #3 37108438e24SVarun Wadekar movz x4, #0x8000, lsl #48 372d0e1094eSEleanor Bonnici msr CORTEX_A57_CPUACTLR_EL1, x4 /* turn off RCG */ 37308438e24SVarun Wadekar isb 37408438e24SVarun Wadekar msr rmr_el3, x3 /* request warm reset */ 37508438e24SVarun Wadekar isb 37608438e24SVarun Wadekar dsb sy 37708438e24SVarun Wadekar1: wfi 37808438e24SVarun Wadekar b 1b 37908438e24SVarun Wadekar 38008438e24SVarun Wadekar /* -------------------------------------------------- 38108438e24SVarun Wadekar * These nops are here so that speculative execution 38208438e24SVarun Wadekar * won't harm us before we are done with warm reset. 38308438e24SVarun Wadekar * -------------------------------------------------- 38408438e24SVarun Wadekar */ 38508438e24SVarun Wadekar .rept 65 38608438e24SVarun Wadekar nop 38708438e24SVarun Wadekar .endr 388*c195fec6SHarvey Hsieh2: 38908438e24SVarun Wadekar /* -------------------------------------------------- 39008438e24SVarun Wadekar * Do not insert instructions here 39108438e24SVarun Wadekar * -------------------------------------------------- 39208438e24SVarun Wadekar */ 39308438e24SVarun Wadekar#endif 39408438e24SVarun Wadekar 39508438e24SVarun Wadekar /* -------------------------------------------------- 39608438e24SVarun Wadekar * Restore OS Lock bit 39708438e24SVarun Wadekar * -------------------------------------------------- 39808438e24SVarun Wadekar */ 39908438e24SVarun Wadekarrestore_oslock: 40008438e24SVarun Wadekar mov x0, #1 40108438e24SVarun Wadekar msr oslar_el1, x0 40208438e24SVarun Wadekar 40308438e24SVarun Wadekar cpu_init_common 40408438e24SVarun Wadekar 40508438e24SVarun Wadekar /* --------------------------------------------------------------------- 40608438e24SVarun Wadekar * The initial state of the Architectural feature trap register 40708438e24SVarun Wadekar * (CPTR_EL3) is unknown and it must be set to a known state. All 40808438e24SVarun Wadekar * feature traps are disabled. Some bits in this register are marked as 40908438e24SVarun Wadekar * Reserved and should not be modified. 41008438e24SVarun Wadekar * 41108438e24SVarun Wadekar * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1 41208438e24SVarun Wadekar * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2. 41308438e24SVarun Wadekar * CPTR_EL3.TTA: This causes access to the Trace functionality to trap 41408438e24SVarun Wadekar * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register 41508438e24SVarun Wadekar * access to trace functionality is not supported, this bit is RES0. 41608438e24SVarun Wadekar * CPTR_EL3.TFP: This causes instructions that access the registers 41708438e24SVarun Wadekar * associated with Floating Point and Advanced SIMD execution to trap 41808438e24SVarun Wadekar * to EL3 when executed from any exception level, unless trapped to EL1 41908438e24SVarun Wadekar * or EL2. 42008438e24SVarun Wadekar * --------------------------------------------------------------------- 42108438e24SVarun Wadekar */ 42208438e24SVarun Wadekar mrs x1, cptr_el3 42308438e24SVarun Wadekar bic w1, w1, #TCPAC_BIT 42408438e24SVarun Wadekar bic w1, w1, #TTA_BIT 42508438e24SVarun Wadekar bic w1, w1, #TFP_BIT 42608438e24SVarun Wadekar msr cptr_el3, x1 42708438e24SVarun Wadekar 42808438e24SVarun Wadekar /* -------------------------------------------------- 42908438e24SVarun Wadekar * Get secure world's entry point and jump to it 43008438e24SVarun Wadekar * -------------------------------------------------- 43108438e24SVarun Wadekar */ 43271cb26eaSVarun Wadekar bl plat_get_my_entrypoint 43308438e24SVarun Wadekar br x0 43408438e24SVarun Wadekarendfunc tegra_secure_entrypoint 43508438e24SVarun Wadekar 43608438e24SVarun Wadekar .data 43708438e24SVarun Wadekar .align 3 43808438e24SVarun Wadekar 43908438e24SVarun Wadekar /* -------------------------------------------------- 44071cb26eaSVarun Wadekar * CPU Secure entry point - resume from suspend 44108438e24SVarun Wadekar * -------------------------------------------------- 44208438e24SVarun Wadekar */ 44371cb26eaSVarun Wadekartegra_sec_entry_point: 44408438e24SVarun Wadekar .quad 0 44508438e24SVarun Wadekar 44608438e24SVarun Wadekar /* -------------------------------------------------- 44708438e24SVarun Wadekar * NS world's cold boot entry point 44808438e24SVarun Wadekar * -------------------------------------------------- 44908438e24SVarun Wadekar */ 45008438e24SVarun Wadekarns_image_entrypoint: 45108438e24SVarun Wadekar .quad 0 45208438e24SVarun Wadekar 45308438e24SVarun Wadekar /* -------------------------------------------------- 45408438e24SVarun Wadekar * BL31's physical base address 45508438e24SVarun Wadekar * -------------------------------------------------- 45608438e24SVarun Wadekar */ 45708438e24SVarun Wadekartegra_bl31_phys_base: 45808438e24SVarun Wadekar .quad 0 459e1084216SVarun Wadekar 460e1084216SVarun Wadekar /* -------------------------------------------------- 461e1084216SVarun Wadekar * UART controller base for console init 462e1084216SVarun Wadekar * -------------------------------------------------- 463e1084216SVarun Wadekar */ 464e1084216SVarun Wadekartegra_console_base: 465e1084216SVarun Wadekar .quad 0 466