108438e24SVarun Wadekar/* 2544c092bSAmbroise Vincent * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3*b1481cffSVarun Wadekar * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 408438e24SVarun Wadekar * 582cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 608438e24SVarun Wadekar */ 708438e24SVarun Wadekar#include <arch.h> 808438e24SVarun Wadekar#include <asm_macros.S> 908438e24SVarun Wadekar#include <assert_macros.S> 1008438e24SVarun Wadekar#include <cpu_macros.S> 1108438e24SVarun Wadekar#include <cortex_a53.h> 12ee1ebbd1SIsla Mitchell#include <cortex_a57.h> 1311bd24beSVarun Wadekar#include <platform_def.h> 1408438e24SVarun Wadekar#include <tegra_def.h> 15c195fec6SHarvey Hsieh#include <tegra_platform.h> 1608438e24SVarun Wadekar 170cd6138dSVarun Wadekar#define MIDR_PN_CORTEX_A57 0xD07 180cd6138dSVarun Wadekar 190cd6138dSVarun Wadekar/******************************************************************************* 200cd6138dSVarun Wadekar * Implementation defined ACTLR_EL3 bit definitions 210cd6138dSVarun Wadekar ******************************************************************************/ 22*b1481cffSVarun Wadekar#define ACTLR_ELx_L2ACTLR_BIT (U(1) << 6) 23*b1481cffSVarun Wadekar#define ACTLR_ELx_L2ECTLR_BIT (U(1) << 5) 24*b1481cffSVarun Wadekar#define ACTLR_ELx_L2CTLR_BIT (U(1) << 4) 25*b1481cffSVarun Wadekar#define ACTLR_ELx_CPUECTLR_BIT (U(1) << 1) 26*b1481cffSVarun Wadekar#define ACTLR_ELx_CPUACTLR_BIT (U(1) << 0) 27*b1481cffSVarun Wadekar#define ACTLR_ELx_ENABLE_ALL_ACCESS (ACTLR_ELx_L2ACTLR_BIT | \ 28*b1481cffSVarun Wadekar ACTLR_ELx_L2ECTLR_BIT | \ 29*b1481cffSVarun Wadekar ACTLR_ELx_L2CTLR_BIT | \ 30*b1481cffSVarun Wadekar ACTLR_ELx_CPUECTLR_BIT | \ 31*b1481cffSVarun Wadekar ACTLR_ELx_CPUACTLR_BIT) 320cd6138dSVarun Wadekar 3308438e24SVarun Wadekar /* Global functions */ 3471cb26eaSVarun Wadekar .globl plat_is_my_cpu_primary 3571cb26eaSVarun Wadekar .globl plat_my_core_pos 3671cb26eaSVarun Wadekar .globl plat_get_my_entrypoint 3708438e24SVarun Wadekar .globl plat_secondary_cold_boot_setup 3808438e24SVarun Wadekar .globl platform_mem_init 3908438e24SVarun Wadekar .globl plat_crash_console_init 4008438e24SVarun Wadekar .globl plat_crash_console_putc 419c675b37SAntonio Nino Diaz .globl plat_crash_console_flush 4208438e24SVarun Wadekar .globl tegra_secure_entrypoint 4308438e24SVarun Wadekar .globl plat_reset_handler 4408438e24SVarun Wadekar 4508438e24SVarun Wadekar /* Global variables */ 4671cb26eaSVarun Wadekar .globl tegra_sec_entry_point 4708438e24SVarun Wadekar .globl ns_image_entrypoint 4808438e24SVarun Wadekar .globl tegra_bl31_phys_base 49e1084216SVarun Wadekar .globl tegra_console_base 5008438e24SVarun Wadekar 5108438e24SVarun Wadekar /* --------------------- 5208438e24SVarun Wadekar * Common CPU init code 5308438e24SVarun Wadekar * --------------------- 5408438e24SVarun Wadekar */ 5508438e24SVarun Wadekar.macro cpu_init_common 5608438e24SVarun Wadekar 570cd6138dSVarun Wadekar /* ------------------------------------------------ 58018b8480SVarun Wadekar * We enable procesor retention, L2/CPUECTLR NS 59018b8480SVarun Wadekar * access and ECC/Parity protection for A57 CPUs 600cd6138dSVarun Wadekar * ------------------------------------------------ 610cd6138dSVarun Wadekar */ 620cd6138dSVarun Wadekar mrs x0, midr_el1 630cd6138dSVarun Wadekar mov x1, #(MIDR_PN_MASK << MIDR_PN_SHIFT) 640cd6138dSVarun Wadekar and x0, x0, x1 650cd6138dSVarun Wadekar lsr x0, x0, #MIDR_PN_SHIFT 660cd6138dSVarun Wadekar cmp x0, #MIDR_PN_CORTEX_A57 670cd6138dSVarun Wadekar b.ne 1f 680cd6138dSVarun Wadekar 69b42192bcSVarun Wadekar /* --------------------------- 70b42192bcSVarun Wadekar * Enable processor retention 71b42192bcSVarun Wadekar * --------------------------- 72b42192bcSVarun Wadekar */ 73fb7d32e5SVarun Wadekar mrs x0, CORTEX_A57_L2ECTLR_EL1 74fb7d32e5SVarun Wadekar mov x1, #RETENTION_ENTRY_TICKS_512 75fb7d32e5SVarun Wadekar bic x0, x0, #CORTEX_A57_L2ECTLR_RET_CTRL_MASK 76b42192bcSVarun Wadekar orr x0, x0, x1 77fb7d32e5SVarun Wadekar msr CORTEX_A57_L2ECTLR_EL1, x0 78b42192bcSVarun Wadekar isb 79b42192bcSVarun Wadekar 80fb7d32e5SVarun Wadekar mrs x0, CORTEX_A57_ECTLR_EL1 81fb7d32e5SVarun Wadekar mov x1, #RETENTION_ENTRY_TICKS_512 82fb7d32e5SVarun Wadekar bic x0, x0, #CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK 83b42192bcSVarun Wadekar orr x0, x0, x1 84fb7d32e5SVarun Wadekar msr CORTEX_A57_ECTLR_EL1, x0 85b42192bcSVarun Wadekar isb 86b42192bcSVarun Wadekar 8708438e24SVarun Wadekar /* ------------------------------------------------------- 8808438e24SVarun Wadekar * Enable L2 and CPU ECTLR RW access from non-secure world 8908438e24SVarun Wadekar * ------------------------------------------------------- 9008438e24SVarun Wadekar */ 9175516c3eSSteven Kao mrs x0, actlr_el3 92*b1481cffSVarun Wadekar mov x1, #ACTLR_ELx_ENABLE_ALL_ACCESS 9375516c3eSSteven Kao orr x0, x0, x1 9408438e24SVarun Wadekar msr actlr_el3, x0 9575516c3eSSteven Kao mrs x0, actlr_el2 96*b1481cffSVarun Wadekar mov x1, #ACTLR_ELx_ENABLE_ALL_ACCESS 9775516c3eSSteven Kao orr x0, x0, x1 9808438e24SVarun Wadekar msr actlr_el2, x0 9908438e24SVarun Wadekar isb 10008438e24SVarun Wadekar 10108438e24SVarun Wadekar /* -------------------------------- 10208438e24SVarun Wadekar * Enable the cycle count register 10308438e24SVarun Wadekar * -------------------------------- 10408438e24SVarun Wadekar */ 1050cd6138dSVarun Wadekar1: mrs x0, pmcr_el0 10608438e24SVarun Wadekar ubfx x0, x0, #11, #5 // read PMCR.N field 10708438e24SVarun Wadekar mov x1, #1 10808438e24SVarun Wadekar lsl x0, x1, x0 10908438e24SVarun Wadekar sub x0, x0, #1 // mask of event counters 11008438e24SVarun Wadekar orr x0, x0, #0x80000000 // disable overflow intrs 11108438e24SVarun Wadekar msr pmintenclr_el1, x0 11208438e24SVarun Wadekar msr pmuserenr_el0, x1 // enable user mode access 11308438e24SVarun Wadekar 11408438e24SVarun Wadekar /* ---------------------------------------------------------------- 11508438e24SVarun Wadekar * Allow non-privileged access to CNTVCT: Set CNTKCTL (Kernel Count 11608438e24SVarun Wadekar * register), bit 1 (EL0VCTEN) to enable access to CNTVCT/CNTFRQ 11708438e24SVarun Wadekar * registers from EL0. 11808438e24SVarun Wadekar * ---------------------------------------------------------------- 11908438e24SVarun Wadekar */ 12008438e24SVarun Wadekar mrs x0, cntkctl_el1 12108438e24SVarun Wadekar orr x0, x0, #EL0VCTEN_BIT 12208438e24SVarun Wadekar msr cntkctl_el1, x0 12308438e24SVarun Wadekar.endm 12408438e24SVarun Wadekar 12508438e24SVarun Wadekar /* ----------------------------------------------------- 12671cb26eaSVarun Wadekar * unsigned int plat_is_my_cpu_primary(void); 12708438e24SVarun Wadekar * 12808438e24SVarun Wadekar * This function checks if this is the Primary CPU 12908438e24SVarun Wadekar * ----------------------------------------------------- 13008438e24SVarun Wadekar */ 13171cb26eaSVarun Wadekarfunc plat_is_my_cpu_primary 13271cb26eaSVarun Wadekar mrs x0, mpidr_el1 13308438e24SVarun Wadekar and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 13408438e24SVarun Wadekar cmp x0, #TEGRA_PRIMARY_CPU 13508438e24SVarun Wadekar cset x0, eq 13608438e24SVarun Wadekar ret 13771cb26eaSVarun Wadekarendfunc plat_is_my_cpu_primary 13808438e24SVarun Wadekar 139b627d083SVarun Wadekar /* ---------------------------------------------------------- 14071cb26eaSVarun Wadekar * unsigned int plat_my_core_pos(void); 14108438e24SVarun Wadekar * 142b627d083SVarun Wadekar * result: CorePos = CoreId + (ClusterId * cpus per cluster) 143b627d083SVarun Wadekar * ---------------------------------------------------------- 14408438e24SVarun Wadekar */ 14571cb26eaSVarun Wadekarfunc plat_my_core_pos 14671cb26eaSVarun Wadekar mrs x0, mpidr_el1 14771cb26eaSVarun Wadekar and x1, x0, #MPIDR_CPU_MASK 14871cb26eaSVarun Wadekar and x0, x0, #MPIDR_CLUSTER_MASK 149b627d083SVarun Wadekar lsr x0, x0, #MPIDR_AFFINITY_BITS 150b627d083SVarun Wadekar mov x2, #PLATFORM_MAX_CPUS_PER_CLUSTER 151b627d083SVarun Wadekar mul x0, x0, x2 152b627d083SVarun Wadekar add x0, x1, x0 15308438e24SVarun Wadekar ret 15471cb26eaSVarun Wadekarendfunc plat_my_core_pos 15571cb26eaSVarun Wadekar 15671cb26eaSVarun Wadekar /* ----------------------------------------------------- 15771cb26eaSVarun Wadekar * unsigned long plat_get_my_entrypoint (void); 15871cb26eaSVarun Wadekar * 15971cb26eaSVarun Wadekar * Main job of this routine is to distinguish between 16071cb26eaSVarun Wadekar * a cold and warm boot. If the tegra_sec_entry_point for 16171cb26eaSVarun Wadekar * this CPU is present, then it's a warm boot. 16271cb26eaSVarun Wadekar * 16371cb26eaSVarun Wadekar * ----------------------------------------------------- 16471cb26eaSVarun Wadekar */ 16571cb26eaSVarun Wadekarfunc plat_get_my_entrypoint 16671cb26eaSVarun Wadekar adr x1, tegra_sec_entry_point 16771cb26eaSVarun Wadekar ldr x0, [x1] 16871cb26eaSVarun Wadekar ret 16971cb26eaSVarun Wadekarendfunc plat_get_my_entrypoint 17008438e24SVarun Wadekar 17108438e24SVarun Wadekar /* ----------------------------------------------------- 172bde81dccSVarun Wadekar * int platform_get_core_pos(int mpidr); 173bde81dccSVarun Wadekar * 174b627d083SVarun Wadekar * result: CorePos = (ClusterId * cpus per cluster) + 175bde81dccSVarun Wadekar * CoreId 176bde81dccSVarun Wadekar * ----------------------------------------------------- 177bde81dccSVarun Wadekar */ 178bde81dccSVarun Wadekarfunc platform_get_core_pos 179bde81dccSVarun Wadekar and x1, x0, #MPIDR_CPU_MASK 180bde81dccSVarun Wadekar and x0, x0, #MPIDR_CLUSTER_MASK 181b627d083SVarun Wadekar lsr x0, x0, #MPIDR_AFFINITY_BITS 182b627d083SVarun Wadekar mov x2, #PLATFORM_MAX_CPUS_PER_CLUSTER 183b627d083SVarun Wadekar mul x0, x0, x2 184b627d083SVarun Wadekar add x0, x1, x0 185bde81dccSVarun Wadekar ret 186bde81dccSVarun Wadekarendfunc platform_get_core_pos 187bde81dccSVarun Wadekar 188bde81dccSVarun Wadekar /* ----------------------------------------------------- 18908438e24SVarun Wadekar * void plat_secondary_cold_boot_setup (void); 19008438e24SVarun Wadekar * 19108438e24SVarun Wadekar * This function performs any platform specific actions 19208438e24SVarun Wadekar * needed for a secondary cpu after a cold reset. Right 19308438e24SVarun Wadekar * now this is a stub function. 19408438e24SVarun Wadekar * ----------------------------------------------------- 19508438e24SVarun Wadekar */ 19608438e24SVarun Wadekarfunc plat_secondary_cold_boot_setup 19708438e24SVarun Wadekar mov x0, #0 19808438e24SVarun Wadekar ret 19908438e24SVarun Wadekarendfunc plat_secondary_cold_boot_setup 20008438e24SVarun Wadekar 20108438e24SVarun Wadekar /* -------------------------------------------------------- 20208438e24SVarun Wadekar * void platform_mem_init (void); 20308438e24SVarun Wadekar * 20408438e24SVarun Wadekar * Any memory init, relocation to be done before the 20508438e24SVarun Wadekar * platform boots. Called very early in the boot process. 20608438e24SVarun Wadekar * -------------------------------------------------------- 20708438e24SVarun Wadekar */ 20808438e24SVarun Wadekarfunc platform_mem_init 20908438e24SVarun Wadekar mov x0, #0 21008438e24SVarun Wadekar ret 21108438e24SVarun Wadekarendfunc platform_mem_init 21208438e24SVarun Wadekar 21308438e24SVarun Wadekar /* --------------------------------------------------- 21408438e24SVarun Wadekar * Function to handle a platform reset and store 21508438e24SVarun Wadekar * input parameters passed by BL2. 21608438e24SVarun Wadekar * --------------------------------------------------- 21708438e24SVarun Wadekar */ 21808438e24SVarun Wadekarfunc plat_reset_handler 21908438e24SVarun Wadekar 220939dcf25SVarun Wadekar /* ---------------------------------------------------- 221939dcf25SVarun Wadekar * Verify if we are running from BL31_BASE address 222939dcf25SVarun Wadekar * ---------------------------------------------------- 223939dcf25SVarun Wadekar */ 224939dcf25SVarun Wadekar adr x18, bl31_entrypoint 225939dcf25SVarun Wadekar mov x17, #BL31_BASE 226939dcf25SVarun Wadekar cmp x18, x17 227939dcf25SVarun Wadekar b.eq 1f 228939dcf25SVarun Wadekar 229939dcf25SVarun Wadekar /* ---------------------------------------------------- 230939dcf25SVarun Wadekar * Copy the entire BL31 code to BL31_BASE if we are not 231939dcf25SVarun Wadekar * running from it already 232939dcf25SVarun Wadekar * ---------------------------------------------------- 233939dcf25SVarun Wadekar */ 234939dcf25SVarun Wadekar mov x0, x17 235939dcf25SVarun Wadekar mov x1, x18 236939dcf25SVarun Wadekar mov x2, #BL31_SIZE 237939dcf25SVarun Wadekar_loop16: 238939dcf25SVarun Wadekar cmp x2, #16 239768baf6eSDouglas Raillard b.lo _loop1 240939dcf25SVarun Wadekar ldp x3, x4, [x1], #16 241939dcf25SVarun Wadekar stp x3, x4, [x0], #16 242939dcf25SVarun Wadekar sub x2, x2, #16 243939dcf25SVarun Wadekar b _loop16 244939dcf25SVarun Wadekar /* copy byte per byte */ 245939dcf25SVarun Wadekar_loop1: 246939dcf25SVarun Wadekar cbz x2, _end 247939dcf25SVarun Wadekar ldrb w3, [x1], #1 248939dcf25SVarun Wadekar strb w3, [x0], #1 249939dcf25SVarun Wadekar subs x2, x2, #1 250939dcf25SVarun Wadekar b.ne _loop1 251939dcf25SVarun Wadekar 252939dcf25SVarun Wadekar /* ---------------------------------------------------- 253939dcf25SVarun Wadekar * Jump to BL31_BASE and start execution again 254939dcf25SVarun Wadekar * ---------------------------------------------------- 255939dcf25SVarun Wadekar */ 256939dcf25SVarun Wadekar_end: mov x0, x20 257939dcf25SVarun Wadekar mov x1, x21 258939dcf25SVarun Wadekar br x17 259939dcf25SVarun Wadekar1: 260939dcf25SVarun Wadekar 26108438e24SVarun Wadekar /* ----------------------------------- 26208438e24SVarun Wadekar * derive and save the phys_base addr 26308438e24SVarun Wadekar * ----------------------------------- 26408438e24SVarun Wadekar */ 26508438e24SVarun Wadekar adr x17, tegra_bl31_phys_base 26608438e24SVarun Wadekar ldr x18, [x17] 26708438e24SVarun Wadekar cbnz x18, 1f 26808438e24SVarun Wadekar adr x18, bl31_entrypoint 26908438e24SVarun Wadekar str x18, [x17] 27008438e24SVarun Wadekar 27108438e24SVarun Wadekar1: cpu_init_common 27208438e24SVarun Wadekar 27308438e24SVarun Wadekar ret 27408438e24SVarun Wadekarendfunc plat_reset_handler 27508438e24SVarun Wadekar 27608438e24SVarun Wadekar /* ---------------------------------------- 27708438e24SVarun Wadekar * Secure entrypoint function for CPU boot 27808438e24SVarun Wadekar * ---------------------------------------- 27908438e24SVarun Wadekar */ 28064726e6dSJulius Wernerfunc tegra_secure_entrypoint _align=6 28108438e24SVarun Wadekar 28208438e24SVarun Wadekar#if ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT 28308438e24SVarun Wadekar 284c195fec6SHarvey Hsieh /* -------------------------------------------------------- 285c195fec6SHarvey Hsieh * Skip the invalidate BTB workaround for Tegra210B01 SKUs. 286c195fec6SHarvey Hsieh * -------------------------------------------------------- 287c195fec6SHarvey Hsieh */ 288c195fec6SHarvey Hsieh mov x0, #TEGRA_MISC_BASE 289c195fec6SHarvey Hsieh add x0, x0, #HARDWARE_REVISION_OFFSET 290c195fec6SHarvey Hsieh ldr w1, [x0] 291c195fec6SHarvey Hsieh lsr w1, w1, #CHIP_ID_SHIFT 292c195fec6SHarvey Hsieh and w1, w1, #CHIP_ID_MASK 293c195fec6SHarvey Hsieh cmp w1, #TEGRA_CHIPID_TEGRA21 /* T210? */ 294c195fec6SHarvey Hsieh b.ne 2f 295c195fec6SHarvey Hsieh ldr w1, [x0] 296c195fec6SHarvey Hsieh lsr w1, w1, #MAJOR_VERSION_SHIFT 297c195fec6SHarvey Hsieh and w1, w1, #MAJOR_VERSION_MASK 298c195fec6SHarvey Hsieh cmp w1, #0x02 /* T210 B01? */ 299c195fec6SHarvey Hsieh b.eq 2f 300c195fec6SHarvey Hsieh 30108438e24SVarun Wadekar /* ------------------------------------------------------- 30208438e24SVarun Wadekar * Invalidate BTB along with I$ to remove any stale 30308438e24SVarun Wadekar * entries from the branch predictor array. 30408438e24SVarun Wadekar * ------------------------------------------------------- 30508438e24SVarun Wadekar */ 306d0e1094eSEleanor Bonnici mrs x0, CORTEX_A57_CPUACTLR_EL1 30708438e24SVarun Wadekar orr x0, x0, #1 308d0e1094eSEleanor Bonnici msr CORTEX_A57_CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */ 30908438e24SVarun Wadekar dsb sy 31008438e24SVarun Wadekar isb 31108438e24SVarun Wadekar ic iallu /* actual invalidate */ 31208438e24SVarun Wadekar dsb sy 31308438e24SVarun Wadekar isb 31408438e24SVarun Wadekar 315d0e1094eSEleanor Bonnici mrs x0, CORTEX_A57_CPUACTLR_EL1 31608438e24SVarun Wadekar bic x0, x0, #1 317d0e1094eSEleanor Bonnici msr CORTEX_A57_CPUACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */ 31808438e24SVarun Wadekar dsb sy 31908438e24SVarun Wadekar isb 32008438e24SVarun Wadekar 32108438e24SVarun Wadekar .rept 7 32208438e24SVarun Wadekar nop /* wait */ 32308438e24SVarun Wadekar .endr 32408438e24SVarun Wadekar 32508438e24SVarun Wadekar /* ----------------------------------------------- 32608438e24SVarun Wadekar * Extract OSLK bit and check if it is '1'. This 32708438e24SVarun Wadekar * bit remains '0' for A53 on warm-resets. If '1', 32808438e24SVarun Wadekar * turn off regional clock gating and request warm 32908438e24SVarun Wadekar * reset. 33008438e24SVarun Wadekar * ----------------------------------------------- 33108438e24SVarun Wadekar */ 33208438e24SVarun Wadekar mrs x0, oslsr_el1 33308438e24SVarun Wadekar and x0, x0, #2 33408438e24SVarun Wadekar mrs x1, mpidr_el1 33508438e24SVarun Wadekar bics xzr, x0, x1, lsr #7 /* 0 = slow cluster or warm reset */ 33608438e24SVarun Wadekar b.eq restore_oslock 33708438e24SVarun Wadekar mov x0, xzr 33808438e24SVarun Wadekar msr oslar_el1, x0 /* os lock stays 0 across warm reset */ 33908438e24SVarun Wadekar mov x3, #3 34008438e24SVarun Wadekar movz x4, #0x8000, lsl #48 341d0e1094eSEleanor Bonnici msr CORTEX_A57_CPUACTLR_EL1, x4 /* turn off RCG */ 34208438e24SVarun Wadekar isb 34308438e24SVarun Wadekar msr rmr_el3, x3 /* request warm reset */ 34408438e24SVarun Wadekar isb 34508438e24SVarun Wadekar dsb sy 34608438e24SVarun Wadekar1: wfi 34708438e24SVarun Wadekar b 1b 34808438e24SVarun Wadekar 34908438e24SVarun Wadekar /* -------------------------------------------------- 35008438e24SVarun Wadekar * These nops are here so that speculative execution 35108438e24SVarun Wadekar * won't harm us before we are done with warm reset. 35208438e24SVarun Wadekar * -------------------------------------------------- 35308438e24SVarun Wadekar */ 35408438e24SVarun Wadekar .rept 65 35508438e24SVarun Wadekar nop 35608438e24SVarun Wadekar .endr 357c195fec6SHarvey Hsieh2: 35808438e24SVarun Wadekar /* -------------------------------------------------- 35908438e24SVarun Wadekar * Do not insert instructions here 36008438e24SVarun Wadekar * -------------------------------------------------- 36108438e24SVarun Wadekar */ 36208438e24SVarun Wadekar#endif 36308438e24SVarun Wadekar 36408438e24SVarun Wadekar /* -------------------------------------------------- 36508438e24SVarun Wadekar * Restore OS Lock bit 36608438e24SVarun Wadekar * -------------------------------------------------- 36708438e24SVarun Wadekar */ 36808438e24SVarun Wadekarrestore_oslock: 36908438e24SVarun Wadekar mov x0, #1 37008438e24SVarun Wadekar msr oslar_el1, x0 37108438e24SVarun Wadekar 37208438e24SVarun Wadekar /* -------------------------------------------------- 37308438e24SVarun Wadekar * Get secure world's entry point and jump to it 37408438e24SVarun Wadekar * -------------------------------------------------- 37508438e24SVarun Wadekar */ 37671cb26eaSVarun Wadekar bl plat_get_my_entrypoint 37708438e24SVarun Wadekar br x0 37808438e24SVarun Wadekarendfunc tegra_secure_entrypoint 37908438e24SVarun Wadekar 38008438e24SVarun Wadekar .data 38108438e24SVarun Wadekar .align 3 38208438e24SVarun Wadekar 38308438e24SVarun Wadekar /* -------------------------------------------------- 38471cb26eaSVarun Wadekar * CPU Secure entry point - resume from suspend 38508438e24SVarun Wadekar * -------------------------------------------------- 38608438e24SVarun Wadekar */ 38771cb26eaSVarun Wadekartegra_sec_entry_point: 38808438e24SVarun Wadekar .quad 0 38908438e24SVarun Wadekar 39008438e24SVarun Wadekar /* -------------------------------------------------- 39108438e24SVarun Wadekar * NS world's cold boot entry point 39208438e24SVarun Wadekar * -------------------------------------------------- 39308438e24SVarun Wadekar */ 39408438e24SVarun Wadekarns_image_entrypoint: 39508438e24SVarun Wadekar .quad 0 39608438e24SVarun Wadekar 39708438e24SVarun Wadekar /* -------------------------------------------------- 39808438e24SVarun Wadekar * BL31's physical base address 39908438e24SVarun Wadekar * -------------------------------------------------- 40008438e24SVarun Wadekar */ 40108438e24SVarun Wadekartegra_bl31_phys_base: 40208438e24SVarun Wadekar .quad 0 403e1084216SVarun Wadekar 404e1084216SVarun Wadekar /* -------------------------------------------------- 405e1084216SVarun Wadekar * UART controller base for console init 406e1084216SVarun Wadekar * -------------------------------------------------- 407e1084216SVarun Wadekar */ 408e1084216SVarun Wadekartegra_console_base: 409e1084216SVarun Wadekar .quad 0 410