108438e24SVarun Wadekar/* 2544c092bSAmbroise Vincent * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3b1481cffSVarun Wadekar * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 408438e24SVarun Wadekar * 582cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 608438e24SVarun Wadekar */ 7*a69a1112SVarun Wadekar 808438e24SVarun Wadekar#include <arch.h> 908438e24SVarun Wadekar#include <asm_macros.S> 1008438e24SVarun Wadekar#include <assert_macros.S> 11ee1ebbd1SIsla Mitchell#include <cortex_a57.h> 12*a69a1112SVarun Wadekar#include <cpu_macros.S> 13*a69a1112SVarun Wadekar 1411bd24beSVarun Wadekar#include <platform_def.h> 1508438e24SVarun Wadekar#include <tegra_def.h> 16c195fec6SHarvey Hsieh#include <tegra_platform.h> 1708438e24SVarun Wadekar 180cd6138dSVarun Wadekar#define MIDR_PN_CORTEX_A57 0xD07 190cd6138dSVarun Wadekar 200cd6138dSVarun Wadekar/******************************************************************************* 210cd6138dSVarun Wadekar * Implementation defined ACTLR_EL3 bit definitions 220cd6138dSVarun Wadekar ******************************************************************************/ 23b1481cffSVarun Wadekar#define ACTLR_ELx_L2ACTLR_BIT (U(1) << 6) 24b1481cffSVarun Wadekar#define ACTLR_ELx_L2ECTLR_BIT (U(1) << 5) 25b1481cffSVarun Wadekar#define ACTLR_ELx_L2CTLR_BIT (U(1) << 4) 26b1481cffSVarun Wadekar#define ACTLR_ELx_CPUECTLR_BIT (U(1) << 1) 27b1481cffSVarun Wadekar#define ACTLR_ELx_CPUACTLR_BIT (U(1) << 0) 28b1481cffSVarun Wadekar#define ACTLR_ELx_ENABLE_ALL_ACCESS (ACTLR_ELx_L2ACTLR_BIT | \ 29b1481cffSVarun Wadekar ACTLR_ELx_L2ECTLR_BIT | \ 30b1481cffSVarun Wadekar ACTLR_ELx_L2CTLR_BIT | \ 31b1481cffSVarun Wadekar ACTLR_ELx_CPUECTLR_BIT | \ 32b1481cffSVarun Wadekar ACTLR_ELx_CPUACTLR_BIT) 330cd6138dSVarun Wadekar 3408438e24SVarun Wadekar /* Global functions */ 3571cb26eaSVarun Wadekar .globl plat_is_my_cpu_primary 3671cb26eaSVarun Wadekar .globl plat_my_core_pos 3771cb26eaSVarun Wadekar .globl plat_get_my_entrypoint 3808438e24SVarun Wadekar .globl plat_secondary_cold_boot_setup 3908438e24SVarun Wadekar .globl platform_mem_init 4008438e24SVarun Wadekar .globl plat_crash_console_init 4108438e24SVarun Wadekar .globl plat_crash_console_putc 429c675b37SAntonio Nino Diaz .globl plat_crash_console_flush 430ac1bf72SVarun Wadekar .weak plat_core_pos_by_mpidr 4408438e24SVarun Wadekar .globl tegra_secure_entrypoint 4508438e24SVarun Wadekar .globl plat_reset_handler 4608438e24SVarun Wadekar 4708438e24SVarun Wadekar /* Global variables */ 4871cb26eaSVarun Wadekar .globl tegra_sec_entry_point 4908438e24SVarun Wadekar .globl ns_image_entrypoint 5008438e24SVarun Wadekar .globl tegra_bl31_phys_base 51e1084216SVarun Wadekar .globl tegra_console_base 5208438e24SVarun Wadekar 5308438e24SVarun Wadekar /* --------------------- 5408438e24SVarun Wadekar * Common CPU init code 5508438e24SVarun Wadekar * --------------------- 5608438e24SVarun Wadekar */ 5708438e24SVarun Wadekar.macro cpu_init_common 5808438e24SVarun Wadekar 590cd6138dSVarun Wadekar /* ------------------------------------------------ 60018b8480SVarun Wadekar * We enable procesor retention, L2/CPUECTLR NS 61018b8480SVarun Wadekar * access and ECC/Parity protection for A57 CPUs 620cd6138dSVarun Wadekar * ------------------------------------------------ 630cd6138dSVarun Wadekar */ 640cd6138dSVarun Wadekar mrs x0, midr_el1 650cd6138dSVarun Wadekar mov x1, #(MIDR_PN_MASK << MIDR_PN_SHIFT) 660cd6138dSVarun Wadekar and x0, x0, x1 670cd6138dSVarun Wadekar lsr x0, x0, #MIDR_PN_SHIFT 680cd6138dSVarun Wadekar cmp x0, #MIDR_PN_CORTEX_A57 690cd6138dSVarun Wadekar b.ne 1f 700cd6138dSVarun Wadekar 71b42192bcSVarun Wadekar /* --------------------------- 72b42192bcSVarun Wadekar * Enable processor retention 73b42192bcSVarun Wadekar * --------------------------- 74b42192bcSVarun Wadekar */ 75fb7d32e5SVarun Wadekar mrs x0, CORTEX_A57_L2ECTLR_EL1 76fb7d32e5SVarun Wadekar mov x1, #RETENTION_ENTRY_TICKS_512 77fb7d32e5SVarun Wadekar bic x0, x0, #CORTEX_A57_L2ECTLR_RET_CTRL_MASK 78b42192bcSVarun Wadekar orr x0, x0, x1 79fb7d32e5SVarun Wadekar msr CORTEX_A57_L2ECTLR_EL1, x0 80b42192bcSVarun Wadekar isb 81b42192bcSVarun Wadekar 82fb7d32e5SVarun Wadekar mrs x0, CORTEX_A57_ECTLR_EL1 83fb7d32e5SVarun Wadekar mov x1, #RETENTION_ENTRY_TICKS_512 84fb7d32e5SVarun Wadekar bic x0, x0, #CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK 85b42192bcSVarun Wadekar orr x0, x0, x1 86fb7d32e5SVarun Wadekar msr CORTEX_A57_ECTLR_EL1, x0 87b42192bcSVarun Wadekar isb 88b42192bcSVarun Wadekar 8908438e24SVarun Wadekar /* ------------------------------------------------------- 9008438e24SVarun Wadekar * Enable L2 and CPU ECTLR RW access from non-secure world 9108438e24SVarun Wadekar * ------------------------------------------------------- 9208438e24SVarun Wadekar */ 9375516c3eSSteven Kao mrs x0, actlr_el3 94b1481cffSVarun Wadekar mov x1, #ACTLR_ELx_ENABLE_ALL_ACCESS 9575516c3eSSteven Kao orr x0, x0, x1 9608438e24SVarun Wadekar msr actlr_el3, x0 9775516c3eSSteven Kao mrs x0, actlr_el2 98b1481cffSVarun Wadekar mov x1, #ACTLR_ELx_ENABLE_ALL_ACCESS 9975516c3eSSteven Kao orr x0, x0, x1 10008438e24SVarun Wadekar msr actlr_el2, x0 10108438e24SVarun Wadekar isb 10208438e24SVarun Wadekar 10308438e24SVarun Wadekar /* -------------------------------- 10408438e24SVarun Wadekar * Enable the cycle count register 10508438e24SVarun Wadekar * -------------------------------- 10608438e24SVarun Wadekar */ 1070cd6138dSVarun Wadekar1: mrs x0, pmcr_el0 10808438e24SVarun Wadekar ubfx x0, x0, #11, #5 // read PMCR.N field 10908438e24SVarun Wadekar mov x1, #1 11008438e24SVarun Wadekar lsl x0, x1, x0 11108438e24SVarun Wadekar sub x0, x0, #1 // mask of event counters 11208438e24SVarun Wadekar orr x0, x0, #0x80000000 // disable overflow intrs 11308438e24SVarun Wadekar msr pmintenclr_el1, x0 11408438e24SVarun Wadekar msr pmuserenr_el0, x1 // enable user mode access 11508438e24SVarun Wadekar 11608438e24SVarun Wadekar /* ---------------------------------------------------------------- 11708438e24SVarun Wadekar * Allow non-privileged access to CNTVCT: Set CNTKCTL (Kernel Count 11808438e24SVarun Wadekar * register), bit 1 (EL0VCTEN) to enable access to CNTVCT/CNTFRQ 11908438e24SVarun Wadekar * registers from EL0. 12008438e24SVarun Wadekar * ---------------------------------------------------------------- 12108438e24SVarun Wadekar */ 12208438e24SVarun Wadekar mrs x0, cntkctl_el1 12308438e24SVarun Wadekar orr x0, x0, #EL0VCTEN_BIT 12408438e24SVarun Wadekar msr cntkctl_el1, x0 12508438e24SVarun Wadekar.endm 12608438e24SVarun Wadekar 12708438e24SVarun Wadekar /* ----------------------------------------------------- 12871cb26eaSVarun Wadekar * unsigned int plat_is_my_cpu_primary(void); 12908438e24SVarun Wadekar * 13008438e24SVarun Wadekar * This function checks if this is the Primary CPU 13108438e24SVarun Wadekar * ----------------------------------------------------- 13208438e24SVarun Wadekar */ 13371cb26eaSVarun Wadekarfunc plat_is_my_cpu_primary 13471cb26eaSVarun Wadekar mrs x0, mpidr_el1 13508438e24SVarun Wadekar and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 13608438e24SVarun Wadekar cmp x0, #TEGRA_PRIMARY_CPU 13708438e24SVarun Wadekar cset x0, eq 13808438e24SVarun Wadekar ret 13971cb26eaSVarun Wadekarendfunc plat_is_my_cpu_primary 14008438e24SVarun Wadekar 141b627d083SVarun Wadekar /* ---------------------------------------------------------- 14271cb26eaSVarun Wadekar * unsigned int plat_my_core_pos(void); 14308438e24SVarun Wadekar * 144b627d083SVarun Wadekar * result: CorePos = CoreId + (ClusterId * cpus per cluster) 1453bab03ebSKalyani Chidambaram * Registers clobbered: x0, x8 146b627d083SVarun Wadekar * ---------------------------------------------------------- 14708438e24SVarun Wadekar */ 14871cb26eaSVarun Wadekarfunc plat_my_core_pos 1493bab03ebSKalyani Chidambaram mov x8, x30 15071cb26eaSVarun Wadekar mrs x0, mpidr_el1 1513bab03ebSKalyani Chidambaram bl plat_core_pos_by_mpidr 1523bab03ebSKalyani Chidambaram ret x8 15371cb26eaSVarun Wadekarendfunc plat_my_core_pos 15471cb26eaSVarun Wadekar 15571cb26eaSVarun Wadekar /* ----------------------------------------------------- 15671cb26eaSVarun Wadekar * unsigned long plat_get_my_entrypoint (void); 15771cb26eaSVarun Wadekar * 15871cb26eaSVarun Wadekar * Main job of this routine is to distinguish between 15971cb26eaSVarun Wadekar * a cold and warm boot. If the tegra_sec_entry_point for 16071cb26eaSVarun Wadekar * this CPU is present, then it's a warm boot. 16171cb26eaSVarun Wadekar * 16271cb26eaSVarun Wadekar * ----------------------------------------------------- 16371cb26eaSVarun Wadekar */ 16471cb26eaSVarun Wadekarfunc plat_get_my_entrypoint 16571cb26eaSVarun Wadekar adr x1, tegra_sec_entry_point 16671cb26eaSVarun Wadekar ldr x0, [x1] 16771cb26eaSVarun Wadekar ret 16871cb26eaSVarun Wadekarendfunc plat_get_my_entrypoint 16908438e24SVarun Wadekar 17008438e24SVarun Wadekar /* ----------------------------------------------------- 17108438e24SVarun Wadekar * void plat_secondary_cold_boot_setup (void); 17208438e24SVarun Wadekar * 17308438e24SVarun Wadekar * This function performs any platform specific actions 17408438e24SVarun Wadekar * needed for a secondary cpu after a cold reset. Right 17508438e24SVarun Wadekar * now this is a stub function. 17608438e24SVarun Wadekar * ----------------------------------------------------- 17708438e24SVarun Wadekar */ 17808438e24SVarun Wadekarfunc plat_secondary_cold_boot_setup 17908438e24SVarun Wadekar mov x0, #0 18008438e24SVarun Wadekar ret 18108438e24SVarun Wadekarendfunc plat_secondary_cold_boot_setup 18208438e24SVarun Wadekar 18308438e24SVarun Wadekar /* -------------------------------------------------------- 18408438e24SVarun Wadekar * void platform_mem_init (void); 18508438e24SVarun Wadekar * 18608438e24SVarun Wadekar * Any memory init, relocation to be done before the 18708438e24SVarun Wadekar * platform boots. Called very early in the boot process. 18808438e24SVarun Wadekar * -------------------------------------------------------- 18908438e24SVarun Wadekar */ 19008438e24SVarun Wadekarfunc platform_mem_init 19108438e24SVarun Wadekar mov x0, #0 19208438e24SVarun Wadekar ret 19308438e24SVarun Wadekarendfunc platform_mem_init 19408438e24SVarun Wadekar 19508438e24SVarun Wadekar /* --------------------------------------------------- 19608438e24SVarun Wadekar * Function to handle a platform reset and store 19708438e24SVarun Wadekar * input parameters passed by BL2. 19808438e24SVarun Wadekar * --------------------------------------------------- 19908438e24SVarun Wadekar */ 20008438e24SVarun Wadekarfunc plat_reset_handler 20108438e24SVarun Wadekar 202939dcf25SVarun Wadekar /* ---------------------------------------------------- 203939dcf25SVarun Wadekar * Verify if we are running from BL31_BASE address 204939dcf25SVarun Wadekar * ---------------------------------------------------- 205939dcf25SVarun Wadekar */ 206939dcf25SVarun Wadekar adr x18, bl31_entrypoint 207939dcf25SVarun Wadekar mov x17, #BL31_BASE 208939dcf25SVarun Wadekar cmp x18, x17 209939dcf25SVarun Wadekar b.eq 1f 210939dcf25SVarun Wadekar 211939dcf25SVarun Wadekar /* ---------------------------------------------------- 212939dcf25SVarun Wadekar * Copy the entire BL31 code to BL31_BASE if we are not 213939dcf25SVarun Wadekar * running from it already 214939dcf25SVarun Wadekar * ---------------------------------------------------- 215939dcf25SVarun Wadekar */ 216939dcf25SVarun Wadekar mov x0, x17 217939dcf25SVarun Wadekar mov x1, x18 218939dcf25SVarun Wadekar mov x2, #BL31_SIZE 219939dcf25SVarun Wadekar_loop16: 220939dcf25SVarun Wadekar cmp x2, #16 221768baf6eSDouglas Raillard b.lo _loop1 222939dcf25SVarun Wadekar ldp x3, x4, [x1], #16 223939dcf25SVarun Wadekar stp x3, x4, [x0], #16 224939dcf25SVarun Wadekar sub x2, x2, #16 225939dcf25SVarun Wadekar b _loop16 226939dcf25SVarun Wadekar /* copy byte per byte */ 227939dcf25SVarun Wadekar_loop1: 228939dcf25SVarun Wadekar cbz x2, _end 229939dcf25SVarun Wadekar ldrb w3, [x1], #1 230939dcf25SVarun Wadekar strb w3, [x0], #1 231939dcf25SVarun Wadekar subs x2, x2, #1 232939dcf25SVarun Wadekar b.ne _loop1 233939dcf25SVarun Wadekar 234939dcf25SVarun Wadekar /* ---------------------------------------------------- 235939dcf25SVarun Wadekar * Jump to BL31_BASE and start execution again 236939dcf25SVarun Wadekar * ---------------------------------------------------- 237939dcf25SVarun Wadekar */ 238939dcf25SVarun Wadekar_end: mov x0, x20 239939dcf25SVarun Wadekar mov x1, x21 240939dcf25SVarun Wadekar br x17 241939dcf25SVarun Wadekar1: 242939dcf25SVarun Wadekar 24308438e24SVarun Wadekar /* ----------------------------------- 24408438e24SVarun Wadekar * derive and save the phys_base addr 24508438e24SVarun Wadekar * ----------------------------------- 24608438e24SVarun Wadekar */ 24708438e24SVarun Wadekar adr x17, tegra_bl31_phys_base 24808438e24SVarun Wadekar ldr x18, [x17] 24908438e24SVarun Wadekar cbnz x18, 1f 25008438e24SVarun Wadekar adr x18, bl31_entrypoint 25108438e24SVarun Wadekar str x18, [x17] 25208438e24SVarun Wadekar 25308438e24SVarun Wadekar1: cpu_init_common 25408438e24SVarun Wadekar 25508438e24SVarun Wadekar ret 25608438e24SVarun Wadekarendfunc plat_reset_handler 25708438e24SVarun Wadekar 2580ac1bf72SVarun Wadekar /* ------------------------------------------------------ 2590ac1bf72SVarun Wadekar * int32_t plat_core_pos_by_mpidr(u_register_t mpidr) 2600ac1bf72SVarun Wadekar * 2610ac1bf72SVarun Wadekar * This function implements a part of the critical 2620ac1bf72SVarun Wadekar * interface between the psci generic layer and the 2630ac1bf72SVarun Wadekar * platform that allows the former to query the platform 2640ac1bf72SVarun Wadekar * to convert an MPIDR to a unique linear index. An error 2650ac1bf72SVarun Wadekar * code (-1) is returned in case the MPIDR is invalid. 2660ac1bf72SVarun Wadekar * 2670ac1bf72SVarun Wadekar * Clobbers: x0-x3 2680ac1bf72SVarun Wadekar * ------------------------------------------------------ 2690ac1bf72SVarun Wadekar */ 2700ac1bf72SVarun Wadekarfunc plat_core_pos_by_mpidr 2710ac1bf72SVarun Wadekar lsr x1, x0, #MPIDR_AFF0_SHIFT 2720ac1bf72SVarun Wadekar and x1, x1, #MPIDR_AFFLVL_MASK /* core id */ 2730ac1bf72SVarun Wadekar lsr x2, x0, #MPIDR_AFF1_SHIFT 2740ac1bf72SVarun Wadekar and x2, x2, #MPIDR_AFFLVL_MASK /* cluster id */ 2750ac1bf72SVarun Wadekar 2760ac1bf72SVarun Wadekar /* core_id >= PLATFORM_MAX_CPUS_PER_CLUSTER */ 2770ac1bf72SVarun Wadekar mov x0, #-1 2780ac1bf72SVarun Wadekar cmp x1, #(PLATFORM_MAX_CPUS_PER_CLUSTER - 1) 2790ac1bf72SVarun Wadekar b.gt 1f 2800ac1bf72SVarun Wadekar 2810ac1bf72SVarun Wadekar /* cluster_id >= PLATFORM_CLUSTER_COUNT */ 2820ac1bf72SVarun Wadekar cmp x2, #(PLATFORM_CLUSTER_COUNT - 1) 2830ac1bf72SVarun Wadekar b.gt 1f 2840ac1bf72SVarun Wadekar 2850ac1bf72SVarun Wadekar /* CorePos = CoreId + (ClusterId * cpus per cluster) */ 2860ac1bf72SVarun Wadekar mov x3, #PLATFORM_MAX_CPUS_PER_CLUSTER 2870ac1bf72SVarun Wadekar mul x3, x3, x2 2880ac1bf72SVarun Wadekar add x0, x1, x3 2890ac1bf72SVarun Wadekar 2900ac1bf72SVarun Wadekar1: 2910ac1bf72SVarun Wadekar ret 2920ac1bf72SVarun Wadekarendfunc plat_core_pos_by_mpidr 2930ac1bf72SVarun Wadekar 29408438e24SVarun Wadekar /* ---------------------------------------- 29508438e24SVarun Wadekar * Secure entrypoint function for CPU boot 29608438e24SVarun Wadekar * ---------------------------------------- 29708438e24SVarun Wadekar */ 29864726e6dSJulius Wernerfunc tegra_secure_entrypoint _align=6 29908438e24SVarun Wadekar 30008438e24SVarun Wadekar#if ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT 30108438e24SVarun Wadekar 302c195fec6SHarvey Hsieh /* -------------------------------------------------------- 303c195fec6SHarvey Hsieh * Skip the invalidate BTB workaround for Tegra210B01 SKUs. 304c195fec6SHarvey Hsieh * -------------------------------------------------------- 305c195fec6SHarvey Hsieh */ 306c195fec6SHarvey Hsieh mov x0, #TEGRA_MISC_BASE 307c195fec6SHarvey Hsieh add x0, x0, #HARDWARE_REVISION_OFFSET 308c195fec6SHarvey Hsieh ldr w1, [x0] 309c195fec6SHarvey Hsieh lsr w1, w1, #CHIP_ID_SHIFT 310c195fec6SHarvey Hsieh and w1, w1, #CHIP_ID_MASK 311c195fec6SHarvey Hsieh cmp w1, #TEGRA_CHIPID_TEGRA21 /* T210? */ 312c195fec6SHarvey Hsieh b.ne 2f 313c195fec6SHarvey Hsieh ldr w1, [x0] 314c195fec6SHarvey Hsieh lsr w1, w1, #MAJOR_VERSION_SHIFT 315c195fec6SHarvey Hsieh and w1, w1, #MAJOR_VERSION_MASK 316c195fec6SHarvey Hsieh cmp w1, #0x02 /* T210 B01? */ 317c195fec6SHarvey Hsieh b.eq 2f 318c195fec6SHarvey Hsieh 31908438e24SVarun Wadekar /* ------------------------------------------------------- 32008438e24SVarun Wadekar * Invalidate BTB along with I$ to remove any stale 32108438e24SVarun Wadekar * entries from the branch predictor array. 32208438e24SVarun Wadekar * ------------------------------------------------------- 32308438e24SVarun Wadekar */ 324d0e1094eSEleanor Bonnici mrs x0, CORTEX_A57_CPUACTLR_EL1 32508438e24SVarun Wadekar orr x0, x0, #1 326d0e1094eSEleanor Bonnici msr CORTEX_A57_CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */ 32708438e24SVarun Wadekar dsb sy 32808438e24SVarun Wadekar isb 32908438e24SVarun Wadekar ic iallu /* actual invalidate */ 33008438e24SVarun Wadekar dsb sy 33108438e24SVarun Wadekar isb 33208438e24SVarun Wadekar 333d0e1094eSEleanor Bonnici mrs x0, CORTEX_A57_CPUACTLR_EL1 33408438e24SVarun Wadekar bic x0, x0, #1 335d0e1094eSEleanor Bonnici msr CORTEX_A57_CPUACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */ 33608438e24SVarun Wadekar dsb sy 33708438e24SVarun Wadekar isb 33808438e24SVarun Wadekar 33908438e24SVarun Wadekar .rept 7 34008438e24SVarun Wadekar nop /* wait */ 34108438e24SVarun Wadekar .endr 34208438e24SVarun Wadekar 34308438e24SVarun Wadekar /* ----------------------------------------------- 34408438e24SVarun Wadekar * Extract OSLK bit and check if it is '1'. This 34508438e24SVarun Wadekar * bit remains '0' for A53 on warm-resets. If '1', 34608438e24SVarun Wadekar * turn off regional clock gating and request warm 34708438e24SVarun Wadekar * reset. 34808438e24SVarun Wadekar * ----------------------------------------------- 34908438e24SVarun Wadekar */ 35008438e24SVarun Wadekar mrs x0, oslsr_el1 35108438e24SVarun Wadekar and x0, x0, #2 35208438e24SVarun Wadekar mrs x1, mpidr_el1 35308438e24SVarun Wadekar bics xzr, x0, x1, lsr #7 /* 0 = slow cluster or warm reset */ 35408438e24SVarun Wadekar b.eq restore_oslock 35508438e24SVarun Wadekar mov x0, xzr 35608438e24SVarun Wadekar msr oslar_el1, x0 /* os lock stays 0 across warm reset */ 35708438e24SVarun Wadekar mov x3, #3 35808438e24SVarun Wadekar movz x4, #0x8000, lsl #48 359d0e1094eSEleanor Bonnici msr CORTEX_A57_CPUACTLR_EL1, x4 /* turn off RCG */ 36008438e24SVarun Wadekar isb 36108438e24SVarun Wadekar msr rmr_el3, x3 /* request warm reset */ 36208438e24SVarun Wadekar isb 36308438e24SVarun Wadekar dsb sy 36408438e24SVarun Wadekar1: wfi 36508438e24SVarun Wadekar b 1b 36608438e24SVarun Wadekar 36708438e24SVarun Wadekar /* -------------------------------------------------- 36808438e24SVarun Wadekar * These nops are here so that speculative execution 36908438e24SVarun Wadekar * won't harm us before we are done with warm reset. 37008438e24SVarun Wadekar * -------------------------------------------------- 37108438e24SVarun Wadekar */ 37208438e24SVarun Wadekar .rept 65 37308438e24SVarun Wadekar nop 37408438e24SVarun Wadekar .endr 375c195fec6SHarvey Hsieh2: 37608438e24SVarun Wadekar /* -------------------------------------------------- 37708438e24SVarun Wadekar * Do not insert instructions here 37808438e24SVarun Wadekar * -------------------------------------------------- 37908438e24SVarun Wadekar */ 38008438e24SVarun Wadekar#endif 38108438e24SVarun Wadekar 38208438e24SVarun Wadekar /* -------------------------------------------------- 38308438e24SVarun Wadekar * Restore OS Lock bit 38408438e24SVarun Wadekar * -------------------------------------------------- 38508438e24SVarun Wadekar */ 38608438e24SVarun Wadekarrestore_oslock: 38708438e24SVarun Wadekar mov x0, #1 38808438e24SVarun Wadekar msr oslar_el1, x0 38908438e24SVarun Wadekar 39008438e24SVarun Wadekar /* -------------------------------------------------- 39108438e24SVarun Wadekar * Get secure world's entry point and jump to it 39208438e24SVarun Wadekar * -------------------------------------------------- 39308438e24SVarun Wadekar */ 39471cb26eaSVarun Wadekar bl plat_get_my_entrypoint 39508438e24SVarun Wadekar br x0 39608438e24SVarun Wadekarendfunc tegra_secure_entrypoint 39708438e24SVarun Wadekar 39808438e24SVarun Wadekar .data 39908438e24SVarun Wadekar .align 3 40008438e24SVarun Wadekar 40108438e24SVarun Wadekar /* -------------------------------------------------- 40271cb26eaSVarun Wadekar * CPU Secure entry point - resume from suspend 40308438e24SVarun Wadekar * -------------------------------------------------- 40408438e24SVarun Wadekar */ 40571cb26eaSVarun Wadekartegra_sec_entry_point: 40608438e24SVarun Wadekar .quad 0 40708438e24SVarun Wadekar 40808438e24SVarun Wadekar /* -------------------------------------------------- 40908438e24SVarun Wadekar * NS world's cold boot entry point 41008438e24SVarun Wadekar * -------------------------------------------------- 41108438e24SVarun Wadekar */ 41208438e24SVarun Wadekarns_image_entrypoint: 41308438e24SVarun Wadekar .quad 0 41408438e24SVarun Wadekar 41508438e24SVarun Wadekar /* -------------------------------------------------- 41608438e24SVarun Wadekar * BL31's physical base address 41708438e24SVarun Wadekar * -------------------------------------------------- 41808438e24SVarun Wadekar */ 41908438e24SVarun Wadekartegra_bl31_phys_base: 42008438e24SVarun Wadekar .quad 0 421e1084216SVarun Wadekar 422e1084216SVarun Wadekar /* -------------------------------------------------- 423e1084216SVarun Wadekar * UART controller base for console init 424e1084216SVarun Wadekar * -------------------------------------------------- 425e1084216SVarun Wadekar */ 426e1084216SVarun Wadekartegra_console_base: 427e1084216SVarun Wadekar .quad 0 428