108438e24SVarun Wadekar/* 208438e24SVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 508438e24SVarun Wadekar */ 608438e24SVarun Wadekar#include <arch.h> 708438e24SVarun Wadekar#include <asm_macros.S> 808438e24SVarun Wadekar#include <assert_macros.S> 908438e24SVarun Wadekar#include <cpu_macros.S> 1008438e24SVarun Wadekar#include <cortex_a57.h> 1108438e24SVarun Wadekar#include <cortex_a53.h> 1211bd24beSVarun Wadekar#include <platform_def.h> 1308438e24SVarun Wadekar#include <tegra_def.h> 1408438e24SVarun Wadekar 150cd6138dSVarun Wadekar#define MIDR_PN_CORTEX_A57 0xD07 160cd6138dSVarun Wadekar 170cd6138dSVarun Wadekar/******************************************************************************* 180cd6138dSVarun Wadekar * Implementation defined ACTLR_EL3 bit definitions 190cd6138dSVarun Wadekar ******************************************************************************/ 200cd6138dSVarun Wadekar#define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 210cd6138dSVarun Wadekar#define ACTLR_EL3_L2ECTLR_BIT (1 << 5) 220cd6138dSVarun Wadekar#define ACTLR_EL3_L2CTLR_BIT (1 << 4) 230cd6138dSVarun Wadekar#define ACTLR_EL3_CPUECTLR_BIT (1 << 1) 240cd6138dSVarun Wadekar#define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 250cd6138dSVarun Wadekar#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ 260cd6138dSVarun Wadekar ACTLR_EL3_L2ECTLR_BIT | \ 270cd6138dSVarun Wadekar ACTLR_EL3_L2CTLR_BIT | \ 280cd6138dSVarun Wadekar ACTLR_EL3_CPUECTLR_BIT | \ 290cd6138dSVarun Wadekar ACTLR_EL3_CPUACTLR_BIT) 300cd6138dSVarun Wadekar 3108438e24SVarun Wadekar /* Global functions */ 3271cb26eaSVarun Wadekar .globl plat_is_my_cpu_primary 3371cb26eaSVarun Wadekar .globl plat_my_core_pos 3471cb26eaSVarun Wadekar .globl plat_get_my_entrypoint 3508438e24SVarun Wadekar .globl plat_secondary_cold_boot_setup 3608438e24SVarun Wadekar .globl platform_mem_init 3708438e24SVarun Wadekar .globl plat_crash_console_init 3808438e24SVarun Wadekar .globl plat_crash_console_putc 3908438e24SVarun Wadekar .globl tegra_secure_entrypoint 4008438e24SVarun Wadekar .globl plat_reset_handler 4108438e24SVarun Wadekar 4208438e24SVarun Wadekar /* Global variables */ 4371cb26eaSVarun Wadekar .globl tegra_sec_entry_point 4408438e24SVarun Wadekar .globl ns_image_entrypoint 4508438e24SVarun Wadekar .globl tegra_bl31_phys_base 46e1084216SVarun Wadekar .globl tegra_console_base 47018b8480SVarun Wadekar .globl tegra_enable_l2_ecc_parity_prot 4808438e24SVarun Wadekar 4908438e24SVarun Wadekar /* --------------------- 5008438e24SVarun Wadekar * Common CPU init code 5108438e24SVarun Wadekar * --------------------- 5208438e24SVarun Wadekar */ 5308438e24SVarun Wadekar.macro cpu_init_common 5408438e24SVarun Wadekar 550cd6138dSVarun Wadekar /* ------------------------------------------------ 56018b8480SVarun Wadekar * We enable procesor retention, L2/CPUECTLR NS 57018b8480SVarun Wadekar * access and ECC/Parity protection for A57 CPUs 580cd6138dSVarun Wadekar * ------------------------------------------------ 590cd6138dSVarun Wadekar */ 600cd6138dSVarun Wadekar mrs x0, midr_el1 610cd6138dSVarun Wadekar mov x1, #(MIDR_PN_MASK << MIDR_PN_SHIFT) 620cd6138dSVarun Wadekar and x0, x0, x1 630cd6138dSVarun Wadekar lsr x0, x0, #MIDR_PN_SHIFT 640cd6138dSVarun Wadekar cmp x0, #MIDR_PN_CORTEX_A57 650cd6138dSVarun Wadekar b.ne 1f 660cd6138dSVarun Wadekar 67b42192bcSVarun Wadekar /* --------------------------- 68b42192bcSVarun Wadekar * Enable processor retention 69b42192bcSVarun Wadekar * --------------------------- 70b42192bcSVarun Wadekar */ 71b42192bcSVarun Wadekar mrs x0, L2ECTLR_EL1 72b42192bcSVarun Wadekar mov x1, #RETENTION_ENTRY_TICKS_512 << L2ECTLR_RET_CTRL_SHIFT 73b42192bcSVarun Wadekar bic x0, x0, #L2ECTLR_RET_CTRL_MASK 74b42192bcSVarun Wadekar orr x0, x0, x1 75b42192bcSVarun Wadekar msr L2ECTLR_EL1, x0 76b42192bcSVarun Wadekar isb 77b42192bcSVarun Wadekar 78b42192bcSVarun Wadekar mrs x0, CPUECTLR_EL1 79b42192bcSVarun Wadekar mov x1, #RETENTION_ENTRY_TICKS_512 << CPUECTLR_CPU_RET_CTRL_SHIFT 80b42192bcSVarun Wadekar bic x0, x0, #CPUECTLR_CPU_RET_CTRL_MASK 81b42192bcSVarun Wadekar orr x0, x0, x1 82b42192bcSVarun Wadekar msr CPUECTLR_EL1, x0 83b42192bcSVarun Wadekar isb 84b42192bcSVarun Wadekar 8508438e24SVarun Wadekar /* ------------------------------------------------------- 8608438e24SVarun Wadekar * Enable L2 and CPU ECTLR RW access from non-secure world 8708438e24SVarun Wadekar * ------------------------------------------------------- 8808438e24SVarun Wadekar */ 8908438e24SVarun Wadekar mov x0, #ACTLR_EL3_ENABLE_ALL_ACCESS 9008438e24SVarun Wadekar msr actlr_el3, x0 9108438e24SVarun Wadekar msr actlr_el2, x0 9208438e24SVarun Wadekar isb 9308438e24SVarun Wadekar 94018b8480SVarun Wadekar /* ------------------------------------------------------- 95018b8480SVarun Wadekar * Enable L2 ECC and Parity Protection 96018b8480SVarun Wadekar * ------------------------------------------------------- 97018b8480SVarun Wadekar */ 98018b8480SVarun Wadekar adr x0, tegra_enable_l2_ecc_parity_prot 99018b8480SVarun Wadekar ldr x0, [x0] 100018b8480SVarun Wadekar cbz x0, 1f 101018b8480SVarun Wadekar mrs x0, L2CTLR_EL1 102018b8480SVarun Wadekar and x1, x0, #L2_ECC_PARITY_PROTECTION_BIT 103018b8480SVarun Wadekar cbnz x1, 1f 104018b8480SVarun Wadekar orr x0, x0, #L2_ECC_PARITY_PROTECTION_BIT 105018b8480SVarun Wadekar msr L2CTLR_EL1, x0 106018b8480SVarun Wadekar isb 107018b8480SVarun Wadekar 10808438e24SVarun Wadekar /* -------------------------------- 10908438e24SVarun Wadekar * Enable the cycle count register 11008438e24SVarun Wadekar * -------------------------------- 11108438e24SVarun Wadekar */ 1120cd6138dSVarun Wadekar1: mrs x0, pmcr_el0 11308438e24SVarun Wadekar ubfx x0, x0, #11, #5 // read PMCR.N field 11408438e24SVarun Wadekar mov x1, #1 11508438e24SVarun Wadekar lsl x0, x1, x0 11608438e24SVarun Wadekar sub x0, x0, #1 // mask of event counters 11708438e24SVarun Wadekar orr x0, x0, #0x80000000 // disable overflow intrs 11808438e24SVarun Wadekar msr pmintenclr_el1, x0 11908438e24SVarun Wadekar msr pmuserenr_el0, x1 // enable user mode access 12008438e24SVarun Wadekar 12108438e24SVarun Wadekar /* ---------------------------------------------------------------- 12208438e24SVarun Wadekar * Allow non-privileged access to CNTVCT: Set CNTKCTL (Kernel Count 12308438e24SVarun Wadekar * register), bit 1 (EL0VCTEN) to enable access to CNTVCT/CNTFRQ 12408438e24SVarun Wadekar * registers from EL0. 12508438e24SVarun Wadekar * ---------------------------------------------------------------- 12608438e24SVarun Wadekar */ 12708438e24SVarun Wadekar mrs x0, cntkctl_el1 12808438e24SVarun Wadekar orr x0, x0, #EL0VCTEN_BIT 12908438e24SVarun Wadekar msr cntkctl_el1, x0 13008438e24SVarun Wadekar.endm 13108438e24SVarun Wadekar 13208438e24SVarun Wadekar /* ----------------------------------------------------- 13371cb26eaSVarun Wadekar * unsigned int plat_is_my_cpu_primary(void); 13408438e24SVarun Wadekar * 13508438e24SVarun Wadekar * This function checks if this is the Primary CPU 13608438e24SVarun Wadekar * ----------------------------------------------------- 13708438e24SVarun Wadekar */ 13871cb26eaSVarun Wadekarfunc plat_is_my_cpu_primary 13971cb26eaSVarun Wadekar mrs x0, mpidr_el1 14008438e24SVarun Wadekar and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 14108438e24SVarun Wadekar cmp x0, #TEGRA_PRIMARY_CPU 14208438e24SVarun Wadekar cset x0, eq 14308438e24SVarun Wadekar ret 14471cb26eaSVarun Wadekarendfunc plat_is_my_cpu_primary 14508438e24SVarun Wadekar 14608438e24SVarun Wadekar /* ----------------------------------------------------- 14771cb26eaSVarun Wadekar * unsigned int plat_my_core_pos(void); 14808438e24SVarun Wadekar * 14971cb26eaSVarun Wadekar * result: CorePos = CoreId + (ClusterId << 2) 15008438e24SVarun Wadekar * ----------------------------------------------------- 15108438e24SVarun Wadekar */ 15271cb26eaSVarun Wadekarfunc plat_my_core_pos 15371cb26eaSVarun Wadekar mrs x0, mpidr_el1 15471cb26eaSVarun Wadekar and x1, x0, #MPIDR_CPU_MASK 15571cb26eaSVarun Wadekar and x0, x0, #MPIDR_CLUSTER_MASK 15671cb26eaSVarun Wadekar add x0, x1, x0, LSR #6 15708438e24SVarun Wadekar ret 15871cb26eaSVarun Wadekarendfunc plat_my_core_pos 15971cb26eaSVarun Wadekar 16071cb26eaSVarun Wadekar /* ----------------------------------------------------- 16171cb26eaSVarun Wadekar * unsigned long plat_get_my_entrypoint (void); 16271cb26eaSVarun Wadekar * 16371cb26eaSVarun Wadekar * Main job of this routine is to distinguish between 16471cb26eaSVarun Wadekar * a cold and warm boot. If the tegra_sec_entry_point for 16571cb26eaSVarun Wadekar * this CPU is present, then it's a warm boot. 16671cb26eaSVarun Wadekar * 16771cb26eaSVarun Wadekar * ----------------------------------------------------- 16871cb26eaSVarun Wadekar */ 16971cb26eaSVarun Wadekarfunc plat_get_my_entrypoint 17071cb26eaSVarun Wadekar adr x1, tegra_sec_entry_point 17171cb26eaSVarun Wadekar ldr x0, [x1] 17271cb26eaSVarun Wadekar ret 17371cb26eaSVarun Wadekarendfunc plat_get_my_entrypoint 17408438e24SVarun Wadekar 17508438e24SVarun Wadekar /* ----------------------------------------------------- 176bde81dccSVarun Wadekar * int platform_get_core_pos(int mpidr); 177bde81dccSVarun Wadekar * 178bde81dccSVarun Wadekar * With this function: CorePos = (ClusterId * 4) + 179bde81dccSVarun Wadekar * CoreId 180bde81dccSVarun Wadekar * ----------------------------------------------------- 181bde81dccSVarun Wadekar */ 182bde81dccSVarun Wadekarfunc platform_get_core_pos 183bde81dccSVarun Wadekar and x1, x0, #MPIDR_CPU_MASK 184bde81dccSVarun Wadekar and x0, x0, #MPIDR_CLUSTER_MASK 185bde81dccSVarun Wadekar add x0, x1, x0, LSR #6 186bde81dccSVarun Wadekar ret 187bde81dccSVarun Wadekarendfunc platform_get_core_pos 188bde81dccSVarun Wadekar 189bde81dccSVarun Wadekar /* ----------------------------------------------------- 19008438e24SVarun Wadekar * void plat_secondary_cold_boot_setup (void); 19108438e24SVarun Wadekar * 19208438e24SVarun Wadekar * This function performs any platform specific actions 19308438e24SVarun Wadekar * needed for a secondary cpu after a cold reset. Right 19408438e24SVarun Wadekar * now this is a stub function. 19508438e24SVarun Wadekar * ----------------------------------------------------- 19608438e24SVarun Wadekar */ 19708438e24SVarun Wadekarfunc plat_secondary_cold_boot_setup 19808438e24SVarun Wadekar mov x0, #0 19908438e24SVarun Wadekar ret 20008438e24SVarun Wadekarendfunc plat_secondary_cold_boot_setup 20108438e24SVarun Wadekar 20208438e24SVarun Wadekar /* -------------------------------------------------------- 20308438e24SVarun Wadekar * void platform_mem_init (void); 20408438e24SVarun Wadekar * 20508438e24SVarun Wadekar * Any memory init, relocation to be done before the 20608438e24SVarun Wadekar * platform boots. Called very early in the boot process. 20708438e24SVarun Wadekar * -------------------------------------------------------- 20808438e24SVarun Wadekar */ 20908438e24SVarun Wadekarfunc platform_mem_init 21008438e24SVarun Wadekar mov x0, #0 21108438e24SVarun Wadekar ret 21208438e24SVarun Wadekarendfunc platform_mem_init 21308438e24SVarun Wadekar 21408438e24SVarun Wadekar /* --------------------------------------------- 21508438e24SVarun Wadekar * int plat_crash_console_init(void) 21608438e24SVarun Wadekar * Function to initialize the crash console 21708438e24SVarun Wadekar * without a C Runtime to print crash report. 2189400b40eSJuan Castillo * Clobber list : x0 - x4 21908438e24SVarun Wadekar * --------------------------------------------- 22008438e24SVarun Wadekar */ 22108438e24SVarun Wadekarfunc plat_crash_console_init 222e87dac6bSVarun Wadekar mov x0, #0 223e87dac6bSVarun Wadekar adr x1, tegra_console_base 224e87dac6bSVarun Wadekar ldr x1, [x1] 225e87dac6bSVarun Wadekar cbz x1, 1f 226e87dac6bSVarun Wadekar mov w0, #1 227e87dac6bSVarun Wadekar1: ret 22808438e24SVarun Wadekarendfunc plat_crash_console_init 22908438e24SVarun Wadekar 23008438e24SVarun Wadekar /* --------------------------------------------- 23108438e24SVarun Wadekar * int plat_crash_console_putc(void) 23208438e24SVarun Wadekar * Function to print a character on the crash 23308438e24SVarun Wadekar * console without a C Runtime. 23408438e24SVarun Wadekar * Clobber list : x1, x2 23508438e24SVarun Wadekar * --------------------------------------------- 23608438e24SVarun Wadekar */ 23708438e24SVarun Wadekarfunc plat_crash_console_putc 238e1084216SVarun Wadekar adr x1, tegra_console_base 239e1084216SVarun Wadekar ldr x1, [x1] 24008438e24SVarun Wadekar b console_core_putc 24108438e24SVarun Wadekarendfunc plat_crash_console_putc 24208438e24SVarun Wadekar 24308438e24SVarun Wadekar /* --------------------------------------------------- 24408438e24SVarun Wadekar * Function to handle a platform reset and store 24508438e24SVarun Wadekar * input parameters passed by BL2. 24608438e24SVarun Wadekar * --------------------------------------------------- 24708438e24SVarun Wadekar */ 24808438e24SVarun Wadekarfunc plat_reset_handler 24908438e24SVarun Wadekar 250939dcf25SVarun Wadekar /* ---------------------------------------------------- 251939dcf25SVarun Wadekar * Verify if we are running from BL31_BASE address 252939dcf25SVarun Wadekar * ---------------------------------------------------- 253939dcf25SVarun Wadekar */ 254939dcf25SVarun Wadekar adr x18, bl31_entrypoint 255939dcf25SVarun Wadekar mov x17, #BL31_BASE 256939dcf25SVarun Wadekar cmp x18, x17 257939dcf25SVarun Wadekar b.eq 1f 258939dcf25SVarun Wadekar 259939dcf25SVarun Wadekar /* ---------------------------------------------------- 260939dcf25SVarun Wadekar * Copy the entire BL31 code to BL31_BASE if we are not 261939dcf25SVarun Wadekar * running from it already 262939dcf25SVarun Wadekar * ---------------------------------------------------- 263939dcf25SVarun Wadekar */ 264939dcf25SVarun Wadekar mov x0, x17 265939dcf25SVarun Wadekar mov x1, x18 266939dcf25SVarun Wadekar mov x2, #BL31_SIZE 267939dcf25SVarun Wadekar_loop16: 268939dcf25SVarun Wadekar cmp x2, #16 269768baf6eSDouglas Raillard b.lo _loop1 270939dcf25SVarun Wadekar ldp x3, x4, [x1], #16 271939dcf25SVarun Wadekar stp x3, x4, [x0], #16 272939dcf25SVarun Wadekar sub x2, x2, #16 273939dcf25SVarun Wadekar b _loop16 274939dcf25SVarun Wadekar /* copy byte per byte */ 275939dcf25SVarun Wadekar_loop1: 276939dcf25SVarun Wadekar cbz x2, _end 277939dcf25SVarun Wadekar ldrb w3, [x1], #1 278939dcf25SVarun Wadekar strb w3, [x0], #1 279939dcf25SVarun Wadekar subs x2, x2, #1 280939dcf25SVarun Wadekar b.ne _loop1 281939dcf25SVarun Wadekar 282939dcf25SVarun Wadekar /* ---------------------------------------------------- 283939dcf25SVarun Wadekar * Jump to BL31_BASE and start execution again 284939dcf25SVarun Wadekar * ---------------------------------------------------- 285939dcf25SVarun Wadekar */ 286939dcf25SVarun Wadekar_end: mov x0, x20 287939dcf25SVarun Wadekar mov x1, x21 288939dcf25SVarun Wadekar br x17 289939dcf25SVarun Wadekar1: 290939dcf25SVarun Wadekar 29108438e24SVarun Wadekar /* ----------------------------------- 29208438e24SVarun Wadekar * derive and save the phys_base addr 29308438e24SVarun Wadekar * ----------------------------------- 29408438e24SVarun Wadekar */ 29508438e24SVarun Wadekar adr x17, tegra_bl31_phys_base 29608438e24SVarun Wadekar ldr x18, [x17] 29708438e24SVarun Wadekar cbnz x18, 1f 29808438e24SVarun Wadekar adr x18, bl31_entrypoint 29908438e24SVarun Wadekar str x18, [x17] 30008438e24SVarun Wadekar 30108438e24SVarun Wadekar1: cpu_init_common 30208438e24SVarun Wadekar 30308438e24SVarun Wadekar ret 30408438e24SVarun Wadekarendfunc plat_reset_handler 30508438e24SVarun Wadekar 30608438e24SVarun Wadekar /* ---------------------------------------- 30708438e24SVarun Wadekar * Secure entrypoint function for CPU boot 30808438e24SVarun Wadekar * ---------------------------------------- 30908438e24SVarun Wadekar */ 31008438e24SVarun Wadekar .align 6 31108438e24SVarun Wadekarfunc tegra_secure_entrypoint 31208438e24SVarun Wadekar 31308438e24SVarun Wadekar#if ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT 31408438e24SVarun Wadekar 31508438e24SVarun Wadekar /* ------------------------------------------------------- 31608438e24SVarun Wadekar * Invalidate BTB along with I$ to remove any stale 31708438e24SVarun Wadekar * entries from the branch predictor array. 31808438e24SVarun Wadekar * ------------------------------------------------------- 31908438e24SVarun Wadekar */ 32008438e24SVarun Wadekar mrs x0, CPUACTLR_EL1 32108438e24SVarun Wadekar orr x0, x0, #1 32208438e24SVarun Wadekar msr CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */ 32308438e24SVarun Wadekar dsb sy 32408438e24SVarun Wadekar isb 32508438e24SVarun Wadekar ic iallu /* actual invalidate */ 32608438e24SVarun Wadekar dsb sy 32708438e24SVarun Wadekar isb 32808438e24SVarun Wadekar 32908438e24SVarun Wadekar mrs x0, CPUACTLR_EL1 33008438e24SVarun Wadekar bic x0, x0, #1 33108438e24SVarun Wadekar msr CPUACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */ 33208438e24SVarun Wadekar dsb sy 33308438e24SVarun Wadekar isb 33408438e24SVarun Wadekar 33508438e24SVarun Wadekar .rept 7 33608438e24SVarun Wadekar nop /* wait */ 33708438e24SVarun Wadekar .endr 33808438e24SVarun Wadekar 33908438e24SVarun Wadekar /* ----------------------------------------------- 34008438e24SVarun Wadekar * Extract OSLK bit and check if it is '1'. This 34108438e24SVarun Wadekar * bit remains '0' for A53 on warm-resets. If '1', 34208438e24SVarun Wadekar * turn off regional clock gating and request warm 34308438e24SVarun Wadekar * reset. 34408438e24SVarun Wadekar * ----------------------------------------------- 34508438e24SVarun Wadekar */ 34608438e24SVarun Wadekar mrs x0, oslsr_el1 34708438e24SVarun Wadekar and x0, x0, #2 34808438e24SVarun Wadekar mrs x1, mpidr_el1 34908438e24SVarun Wadekar bics xzr, x0, x1, lsr #7 /* 0 = slow cluster or warm reset */ 35008438e24SVarun Wadekar b.eq restore_oslock 35108438e24SVarun Wadekar mov x0, xzr 35208438e24SVarun Wadekar msr oslar_el1, x0 /* os lock stays 0 across warm reset */ 35308438e24SVarun Wadekar mov x3, #3 35408438e24SVarun Wadekar movz x4, #0x8000, lsl #48 35508438e24SVarun Wadekar msr CPUACTLR_EL1, x4 /* turn off RCG */ 35608438e24SVarun Wadekar isb 35708438e24SVarun Wadekar msr rmr_el3, x3 /* request warm reset */ 35808438e24SVarun Wadekar isb 35908438e24SVarun Wadekar dsb sy 36008438e24SVarun Wadekar1: wfi 36108438e24SVarun Wadekar b 1b 36208438e24SVarun Wadekar 36308438e24SVarun Wadekar /* -------------------------------------------------- 36408438e24SVarun Wadekar * These nops are here so that speculative execution 36508438e24SVarun Wadekar * won't harm us before we are done with warm reset. 36608438e24SVarun Wadekar * -------------------------------------------------- 36708438e24SVarun Wadekar */ 36808438e24SVarun Wadekar .rept 65 36908438e24SVarun Wadekar nop 37008438e24SVarun Wadekar .endr 37108438e24SVarun Wadekar 37208438e24SVarun Wadekar /* -------------------------------------------------- 37308438e24SVarun Wadekar * Do not insert instructions here 37408438e24SVarun Wadekar * -------------------------------------------------- 37508438e24SVarun Wadekar */ 37608438e24SVarun Wadekar#endif 37708438e24SVarun Wadekar 37808438e24SVarun Wadekar /* -------------------------------------------------- 37908438e24SVarun Wadekar * Restore OS Lock bit 38008438e24SVarun Wadekar * -------------------------------------------------- 38108438e24SVarun Wadekar */ 38208438e24SVarun Wadekarrestore_oslock: 38308438e24SVarun Wadekar mov x0, #1 38408438e24SVarun Wadekar msr oslar_el1, x0 38508438e24SVarun Wadekar 38608438e24SVarun Wadekar cpu_init_common 38708438e24SVarun Wadekar 38808438e24SVarun Wadekar /* --------------------------------------------------------------------- 38908438e24SVarun Wadekar * The initial state of the Architectural feature trap register 39008438e24SVarun Wadekar * (CPTR_EL3) is unknown and it must be set to a known state. All 39108438e24SVarun Wadekar * feature traps are disabled. Some bits in this register are marked as 39208438e24SVarun Wadekar * Reserved and should not be modified. 39308438e24SVarun Wadekar * 39408438e24SVarun Wadekar * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1 39508438e24SVarun Wadekar * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2. 39608438e24SVarun Wadekar * CPTR_EL3.TTA: This causes access to the Trace functionality to trap 39708438e24SVarun Wadekar * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register 39808438e24SVarun Wadekar * access to trace functionality is not supported, this bit is RES0. 39908438e24SVarun Wadekar * CPTR_EL3.TFP: This causes instructions that access the registers 40008438e24SVarun Wadekar * associated with Floating Point and Advanced SIMD execution to trap 40108438e24SVarun Wadekar * to EL3 when executed from any exception level, unless trapped to EL1 40208438e24SVarun Wadekar * or EL2. 40308438e24SVarun Wadekar * --------------------------------------------------------------------- 40408438e24SVarun Wadekar */ 40508438e24SVarun Wadekar mrs x1, cptr_el3 40608438e24SVarun Wadekar bic w1, w1, #TCPAC_BIT 40708438e24SVarun Wadekar bic w1, w1, #TTA_BIT 40808438e24SVarun Wadekar bic w1, w1, #TFP_BIT 40908438e24SVarun Wadekar msr cptr_el3, x1 41008438e24SVarun Wadekar 41108438e24SVarun Wadekar /* -------------------------------------------------- 41208438e24SVarun Wadekar * Get secure world's entry point and jump to it 41308438e24SVarun Wadekar * -------------------------------------------------- 41408438e24SVarun Wadekar */ 41571cb26eaSVarun Wadekar bl plat_get_my_entrypoint 41608438e24SVarun Wadekar br x0 41708438e24SVarun Wadekarendfunc tegra_secure_entrypoint 41808438e24SVarun Wadekar 41908438e24SVarun Wadekar .data 42008438e24SVarun Wadekar .align 3 42108438e24SVarun Wadekar 42208438e24SVarun Wadekar /* -------------------------------------------------- 42371cb26eaSVarun Wadekar * CPU Secure entry point - resume from suspend 42408438e24SVarun Wadekar * -------------------------------------------------- 42508438e24SVarun Wadekar */ 42671cb26eaSVarun Wadekartegra_sec_entry_point: 42708438e24SVarun Wadekar .quad 0 42808438e24SVarun Wadekar 42908438e24SVarun Wadekar /* -------------------------------------------------- 43008438e24SVarun Wadekar * NS world's cold boot entry point 43108438e24SVarun Wadekar * -------------------------------------------------- 43208438e24SVarun Wadekar */ 43308438e24SVarun Wadekarns_image_entrypoint: 43408438e24SVarun Wadekar .quad 0 43508438e24SVarun Wadekar 43608438e24SVarun Wadekar /* -------------------------------------------------- 43708438e24SVarun Wadekar * BL31's physical base address 43808438e24SVarun Wadekar * -------------------------------------------------- 43908438e24SVarun Wadekar */ 44008438e24SVarun Wadekartegra_bl31_phys_base: 44108438e24SVarun Wadekar .quad 0 442e1084216SVarun Wadekar 443e1084216SVarun Wadekar /* -------------------------------------------------- 444e1084216SVarun Wadekar * UART controller base for console init 445e1084216SVarun Wadekar * -------------------------------------------------- 446e1084216SVarun Wadekar */ 447e1084216SVarun Wadekartegra_console_base: 448e1084216SVarun Wadekar .quad 0 449018b8480SVarun Wadekar 450018b8480SVarun Wadekar /* -------------------------------------------------- 451018b8480SVarun Wadekar * Enable L2 ECC and Parity Protection 452018b8480SVarun Wadekar * -------------------------------------------------- 453018b8480SVarun Wadekar */ 454018b8480SVarun Wadekartegra_enable_l2_ecc_parity_prot: 455018b8480SVarun Wadekar .quad 0 456