108438e24SVarun Wadekar/* 29c675b37SAntonio Nino Diaz * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 508438e24SVarun Wadekar */ 608438e24SVarun Wadekar#include <arch.h> 708438e24SVarun Wadekar#include <asm_macros.S> 808438e24SVarun Wadekar#include <assert_macros.S> 908438e24SVarun Wadekar#include <cpu_macros.S> 1008438e24SVarun Wadekar#include <cortex_a53.h> 11ee1ebbd1SIsla Mitchell#include <cortex_a57.h> 1211bd24beSVarun Wadekar#include <platform_def.h> 1308438e24SVarun Wadekar#include <tegra_def.h> 14c195fec6SHarvey Hsieh#include <tegra_platform.h> 1508438e24SVarun Wadekar 160cd6138dSVarun Wadekar#define MIDR_PN_CORTEX_A57 0xD07 170cd6138dSVarun Wadekar 180cd6138dSVarun Wadekar/******************************************************************************* 190cd6138dSVarun Wadekar * Implementation defined ACTLR_EL3 bit definitions 200cd6138dSVarun Wadekar ******************************************************************************/ 21*75516c3eSSteven Kao#define ACTLR_EL3_L2ACTLR_BIT (U(1) << 6) 22*75516c3eSSteven Kao#define ACTLR_EL3_L2ECTLR_BIT (U(1) << 5) 23*75516c3eSSteven Kao#define ACTLR_EL3_L2CTLR_BIT (U(1) << 4) 24*75516c3eSSteven Kao#define ACTLR_EL3_CPUECTLR_BIT (U(1) << 1) 25*75516c3eSSteven Kao#define ACTLR_EL3_CPUACTLR_BIT (U(1) << 0) 26*75516c3eSSteven Kao#define ACTLR_EL3_ENABLE_ALL_MASK (ACTLR_EL3_L2ACTLR_BIT | \ 27*75516c3eSSteven Kao ACTLR_EL3_L2ECTLR_BIT | \ 28*75516c3eSSteven Kao ACTLR_EL3_L2CTLR_BIT | \ 29*75516c3eSSteven Kao ACTLR_EL3_CPUECTLR_BIT | \ 30*75516c3eSSteven Kao ACTLR_EL3_CPUACTLR_BIT) 310cd6138dSVarun Wadekar#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ 320cd6138dSVarun Wadekar ACTLR_EL3_L2ECTLR_BIT | \ 330cd6138dSVarun Wadekar ACTLR_EL3_L2CTLR_BIT | \ 340cd6138dSVarun Wadekar ACTLR_EL3_CPUECTLR_BIT | \ 350cd6138dSVarun Wadekar ACTLR_EL3_CPUACTLR_BIT) 360cd6138dSVarun Wadekar 3708438e24SVarun Wadekar /* Global functions */ 3871cb26eaSVarun Wadekar .globl plat_is_my_cpu_primary 3971cb26eaSVarun Wadekar .globl plat_my_core_pos 4071cb26eaSVarun Wadekar .globl plat_get_my_entrypoint 4108438e24SVarun Wadekar .globl plat_secondary_cold_boot_setup 4208438e24SVarun Wadekar .globl platform_mem_init 4308438e24SVarun Wadekar .globl plat_crash_console_init 4408438e24SVarun Wadekar .globl plat_crash_console_putc 459c675b37SAntonio Nino Diaz .globl plat_crash_console_flush 4608438e24SVarun Wadekar .globl tegra_secure_entrypoint 4708438e24SVarun Wadekar .globl plat_reset_handler 4808438e24SVarun Wadekar 4908438e24SVarun Wadekar /* Global variables */ 5071cb26eaSVarun Wadekar .globl tegra_sec_entry_point 5108438e24SVarun Wadekar .globl ns_image_entrypoint 5208438e24SVarun Wadekar .globl tegra_bl31_phys_base 53e1084216SVarun Wadekar .globl tegra_console_base 5408438e24SVarun Wadekar 5508438e24SVarun Wadekar /* --------------------- 5608438e24SVarun Wadekar * Common CPU init code 5708438e24SVarun Wadekar * --------------------- 5808438e24SVarun Wadekar */ 5908438e24SVarun Wadekar.macro cpu_init_common 6008438e24SVarun Wadekar 610cd6138dSVarun Wadekar /* ------------------------------------------------ 62018b8480SVarun Wadekar * We enable procesor retention, L2/CPUECTLR NS 63018b8480SVarun Wadekar * access and ECC/Parity protection for A57 CPUs 640cd6138dSVarun Wadekar * ------------------------------------------------ 650cd6138dSVarun Wadekar */ 660cd6138dSVarun Wadekar mrs x0, midr_el1 670cd6138dSVarun Wadekar mov x1, #(MIDR_PN_MASK << MIDR_PN_SHIFT) 680cd6138dSVarun Wadekar and x0, x0, x1 690cd6138dSVarun Wadekar lsr x0, x0, #MIDR_PN_SHIFT 700cd6138dSVarun Wadekar cmp x0, #MIDR_PN_CORTEX_A57 710cd6138dSVarun Wadekar b.ne 1f 720cd6138dSVarun Wadekar 73b42192bcSVarun Wadekar /* --------------------------- 74b42192bcSVarun Wadekar * Enable processor retention 75b42192bcSVarun Wadekar * --------------------------- 76b42192bcSVarun Wadekar */ 77fb7d32e5SVarun Wadekar mrs x0, CORTEX_A57_L2ECTLR_EL1 78fb7d32e5SVarun Wadekar mov x1, #RETENTION_ENTRY_TICKS_512 79fb7d32e5SVarun Wadekar bic x0, x0, #CORTEX_A57_L2ECTLR_RET_CTRL_MASK 80b42192bcSVarun Wadekar orr x0, x0, x1 81fb7d32e5SVarun Wadekar msr CORTEX_A57_L2ECTLR_EL1, x0 82b42192bcSVarun Wadekar isb 83b42192bcSVarun Wadekar 84fb7d32e5SVarun Wadekar mrs x0, CORTEX_A57_ECTLR_EL1 85fb7d32e5SVarun Wadekar mov x1, #RETENTION_ENTRY_TICKS_512 86fb7d32e5SVarun Wadekar bic x0, x0, #CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK 87b42192bcSVarun Wadekar orr x0, x0, x1 88fb7d32e5SVarun Wadekar msr CORTEX_A57_ECTLR_EL1, x0 89b42192bcSVarun Wadekar isb 90b42192bcSVarun Wadekar 9108438e24SVarun Wadekar /* ------------------------------------------------------- 9208438e24SVarun Wadekar * Enable L2 and CPU ECTLR RW access from non-secure world 9308438e24SVarun Wadekar * ------------------------------------------------------- 9408438e24SVarun Wadekar */ 95*75516c3eSSteven Kao mrs x0, actlr_el3 96*75516c3eSSteven Kao mov x1, #ACTLR_EL3_ENABLE_ALL_MASK 97*75516c3eSSteven Kao bic x0, x0, x1 98*75516c3eSSteven Kao mov x1, #ACTLR_EL3_ENABLE_ALL_ACCESS 99*75516c3eSSteven Kao orr x0, x0, x1 10008438e24SVarun Wadekar msr actlr_el3, x0 101*75516c3eSSteven Kao mrs x0, actlr_el2 102*75516c3eSSteven Kao mov x1, #ACTLR_EL3_ENABLE_ALL_MASK 103*75516c3eSSteven Kao bic x0, x0, x1 104*75516c3eSSteven Kao mov x1, #ACTLR_EL3_ENABLE_ALL_ACCESS 105*75516c3eSSteven Kao orr x0, x0, x1 10608438e24SVarun Wadekar msr actlr_el2, x0 10708438e24SVarun Wadekar isb 10808438e24SVarun Wadekar 10908438e24SVarun Wadekar /* -------------------------------- 11008438e24SVarun Wadekar * Enable the cycle count register 11108438e24SVarun Wadekar * -------------------------------- 11208438e24SVarun Wadekar */ 1130cd6138dSVarun Wadekar1: mrs x0, pmcr_el0 11408438e24SVarun Wadekar ubfx x0, x0, #11, #5 // read PMCR.N field 11508438e24SVarun Wadekar mov x1, #1 11608438e24SVarun Wadekar lsl x0, x1, x0 11708438e24SVarun Wadekar sub x0, x0, #1 // mask of event counters 11808438e24SVarun Wadekar orr x0, x0, #0x80000000 // disable overflow intrs 11908438e24SVarun Wadekar msr pmintenclr_el1, x0 12008438e24SVarun Wadekar msr pmuserenr_el0, x1 // enable user mode access 12108438e24SVarun Wadekar 12208438e24SVarun Wadekar /* ---------------------------------------------------------------- 12308438e24SVarun Wadekar * Allow non-privileged access to CNTVCT: Set CNTKCTL (Kernel Count 12408438e24SVarun Wadekar * register), bit 1 (EL0VCTEN) to enable access to CNTVCT/CNTFRQ 12508438e24SVarun Wadekar * registers from EL0. 12608438e24SVarun Wadekar * ---------------------------------------------------------------- 12708438e24SVarun Wadekar */ 12808438e24SVarun Wadekar mrs x0, cntkctl_el1 12908438e24SVarun Wadekar orr x0, x0, #EL0VCTEN_BIT 13008438e24SVarun Wadekar msr cntkctl_el1, x0 13108438e24SVarun Wadekar.endm 13208438e24SVarun Wadekar 13308438e24SVarun Wadekar /* ----------------------------------------------------- 13471cb26eaSVarun Wadekar * unsigned int plat_is_my_cpu_primary(void); 13508438e24SVarun Wadekar * 13608438e24SVarun Wadekar * This function checks if this is the Primary CPU 13708438e24SVarun Wadekar * ----------------------------------------------------- 13808438e24SVarun Wadekar */ 13971cb26eaSVarun Wadekarfunc plat_is_my_cpu_primary 14071cb26eaSVarun Wadekar mrs x0, mpidr_el1 14108438e24SVarun Wadekar and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 14208438e24SVarun Wadekar cmp x0, #TEGRA_PRIMARY_CPU 14308438e24SVarun Wadekar cset x0, eq 14408438e24SVarun Wadekar ret 14571cb26eaSVarun Wadekarendfunc plat_is_my_cpu_primary 14608438e24SVarun Wadekar 14708438e24SVarun Wadekar /* ----------------------------------------------------- 14871cb26eaSVarun Wadekar * unsigned int plat_my_core_pos(void); 14908438e24SVarun Wadekar * 15071cb26eaSVarun Wadekar * result: CorePos = CoreId + (ClusterId << 2) 15108438e24SVarun Wadekar * ----------------------------------------------------- 15208438e24SVarun Wadekar */ 15371cb26eaSVarun Wadekarfunc plat_my_core_pos 15471cb26eaSVarun Wadekar mrs x0, mpidr_el1 15571cb26eaSVarun Wadekar and x1, x0, #MPIDR_CPU_MASK 15671cb26eaSVarun Wadekar and x0, x0, #MPIDR_CLUSTER_MASK 15771cb26eaSVarun Wadekar add x0, x1, x0, LSR #6 15808438e24SVarun Wadekar ret 15971cb26eaSVarun Wadekarendfunc plat_my_core_pos 16071cb26eaSVarun Wadekar 16171cb26eaSVarun Wadekar /* ----------------------------------------------------- 16271cb26eaSVarun Wadekar * unsigned long plat_get_my_entrypoint (void); 16371cb26eaSVarun Wadekar * 16471cb26eaSVarun Wadekar * Main job of this routine is to distinguish between 16571cb26eaSVarun Wadekar * a cold and warm boot. If the tegra_sec_entry_point for 16671cb26eaSVarun Wadekar * this CPU is present, then it's a warm boot. 16771cb26eaSVarun Wadekar * 16871cb26eaSVarun Wadekar * ----------------------------------------------------- 16971cb26eaSVarun Wadekar */ 17071cb26eaSVarun Wadekarfunc plat_get_my_entrypoint 17171cb26eaSVarun Wadekar adr x1, tegra_sec_entry_point 17271cb26eaSVarun Wadekar ldr x0, [x1] 17371cb26eaSVarun Wadekar ret 17471cb26eaSVarun Wadekarendfunc plat_get_my_entrypoint 17508438e24SVarun Wadekar 17608438e24SVarun Wadekar /* ----------------------------------------------------- 177bde81dccSVarun Wadekar * int platform_get_core_pos(int mpidr); 178bde81dccSVarun Wadekar * 179bde81dccSVarun Wadekar * With this function: CorePos = (ClusterId * 4) + 180bde81dccSVarun Wadekar * CoreId 181bde81dccSVarun Wadekar * ----------------------------------------------------- 182bde81dccSVarun Wadekar */ 183bde81dccSVarun Wadekarfunc platform_get_core_pos 184bde81dccSVarun Wadekar and x1, x0, #MPIDR_CPU_MASK 185bde81dccSVarun Wadekar and x0, x0, #MPIDR_CLUSTER_MASK 186bde81dccSVarun Wadekar add x0, x1, x0, LSR #6 187bde81dccSVarun Wadekar ret 188bde81dccSVarun Wadekarendfunc platform_get_core_pos 189bde81dccSVarun Wadekar 190bde81dccSVarun Wadekar /* ----------------------------------------------------- 19108438e24SVarun Wadekar * void plat_secondary_cold_boot_setup (void); 19208438e24SVarun Wadekar * 19308438e24SVarun Wadekar * This function performs any platform specific actions 19408438e24SVarun Wadekar * needed for a secondary cpu after a cold reset. Right 19508438e24SVarun Wadekar * now this is a stub function. 19608438e24SVarun Wadekar * ----------------------------------------------------- 19708438e24SVarun Wadekar */ 19808438e24SVarun Wadekarfunc plat_secondary_cold_boot_setup 19908438e24SVarun Wadekar mov x0, #0 20008438e24SVarun Wadekar ret 20108438e24SVarun Wadekarendfunc plat_secondary_cold_boot_setup 20208438e24SVarun Wadekar 20308438e24SVarun Wadekar /* -------------------------------------------------------- 20408438e24SVarun Wadekar * void platform_mem_init (void); 20508438e24SVarun Wadekar * 20608438e24SVarun Wadekar * Any memory init, relocation to be done before the 20708438e24SVarun Wadekar * platform boots. Called very early in the boot process. 20808438e24SVarun Wadekar * -------------------------------------------------------- 20908438e24SVarun Wadekar */ 21008438e24SVarun Wadekarfunc platform_mem_init 21108438e24SVarun Wadekar mov x0, #0 21208438e24SVarun Wadekar ret 21308438e24SVarun Wadekarendfunc platform_mem_init 21408438e24SVarun Wadekar 21508438e24SVarun Wadekar /* --------------------------------------------- 21608438e24SVarun Wadekar * int plat_crash_console_init(void) 21708438e24SVarun Wadekar * Function to initialize the crash console 21808438e24SVarun Wadekar * without a C Runtime to print crash report. 2199400b40eSJuan Castillo * Clobber list : x0 - x4 22008438e24SVarun Wadekar * --------------------------------------------- 22108438e24SVarun Wadekar */ 22208438e24SVarun Wadekarfunc plat_crash_console_init 223e87dac6bSVarun Wadekar mov x0, #0 224e87dac6bSVarun Wadekar adr x1, tegra_console_base 225e87dac6bSVarun Wadekar ldr x1, [x1] 226e87dac6bSVarun Wadekar cbz x1, 1f 227e87dac6bSVarun Wadekar mov w0, #1 228e87dac6bSVarun Wadekar1: ret 22908438e24SVarun Wadekarendfunc plat_crash_console_init 23008438e24SVarun Wadekar 23108438e24SVarun Wadekar /* --------------------------------------------- 23208438e24SVarun Wadekar * int plat_crash_console_putc(void) 23308438e24SVarun Wadekar * Function to print a character on the crash 23408438e24SVarun Wadekar * console without a C Runtime. 23508438e24SVarun Wadekar * Clobber list : x1, x2 23608438e24SVarun Wadekar * --------------------------------------------- 23708438e24SVarun Wadekar */ 23808438e24SVarun Wadekarfunc plat_crash_console_putc 239e1084216SVarun Wadekar adr x1, tegra_console_base 240e1084216SVarun Wadekar ldr x1, [x1] 24108438e24SVarun Wadekar b console_core_putc 24208438e24SVarun Wadekarendfunc plat_crash_console_putc 24308438e24SVarun Wadekar 2449c675b37SAntonio Nino Diaz /* --------------------------------------------- 2459c675b37SAntonio Nino Diaz * int plat_crash_console_flush() 2469c675b37SAntonio Nino Diaz * Function to force a write of all buffered 2479c675b37SAntonio Nino Diaz * data that hasn't been output. 2489c675b37SAntonio Nino Diaz * Out : return -1 on error else return 0. 2499c675b37SAntonio Nino Diaz * Clobber list : x0, x1 2509c675b37SAntonio Nino Diaz * --------------------------------------------- 2519c675b37SAntonio Nino Diaz */ 2529c675b37SAntonio Nino Diazfunc plat_crash_console_flush 2539c675b37SAntonio Nino Diaz adr x0, tegra_console_base 2549c675b37SAntonio Nino Diaz ldr x0, [x0] 2559c675b37SAntonio Nino Diaz b console_core_flush 2569c675b37SAntonio Nino Diazendfunc plat_crash_console_flush 2579c675b37SAntonio Nino Diaz 25808438e24SVarun Wadekar /* --------------------------------------------------- 25908438e24SVarun Wadekar * Function to handle a platform reset and store 26008438e24SVarun Wadekar * input parameters passed by BL2. 26108438e24SVarun Wadekar * --------------------------------------------------- 26208438e24SVarun Wadekar */ 26308438e24SVarun Wadekarfunc plat_reset_handler 26408438e24SVarun Wadekar 265939dcf25SVarun Wadekar /* ---------------------------------------------------- 266939dcf25SVarun Wadekar * Verify if we are running from BL31_BASE address 267939dcf25SVarun Wadekar * ---------------------------------------------------- 268939dcf25SVarun Wadekar */ 269939dcf25SVarun Wadekar adr x18, bl31_entrypoint 270939dcf25SVarun Wadekar mov x17, #BL31_BASE 271939dcf25SVarun Wadekar cmp x18, x17 272939dcf25SVarun Wadekar b.eq 1f 273939dcf25SVarun Wadekar 274939dcf25SVarun Wadekar /* ---------------------------------------------------- 275939dcf25SVarun Wadekar * Copy the entire BL31 code to BL31_BASE if we are not 276939dcf25SVarun Wadekar * running from it already 277939dcf25SVarun Wadekar * ---------------------------------------------------- 278939dcf25SVarun Wadekar */ 279939dcf25SVarun Wadekar mov x0, x17 280939dcf25SVarun Wadekar mov x1, x18 281939dcf25SVarun Wadekar mov x2, #BL31_SIZE 282939dcf25SVarun Wadekar_loop16: 283939dcf25SVarun Wadekar cmp x2, #16 284768baf6eSDouglas Raillard b.lo _loop1 285939dcf25SVarun Wadekar ldp x3, x4, [x1], #16 286939dcf25SVarun Wadekar stp x3, x4, [x0], #16 287939dcf25SVarun Wadekar sub x2, x2, #16 288939dcf25SVarun Wadekar b _loop16 289939dcf25SVarun Wadekar /* copy byte per byte */ 290939dcf25SVarun Wadekar_loop1: 291939dcf25SVarun Wadekar cbz x2, _end 292939dcf25SVarun Wadekar ldrb w3, [x1], #1 293939dcf25SVarun Wadekar strb w3, [x0], #1 294939dcf25SVarun Wadekar subs x2, x2, #1 295939dcf25SVarun Wadekar b.ne _loop1 296939dcf25SVarun Wadekar 297939dcf25SVarun Wadekar /* ---------------------------------------------------- 298939dcf25SVarun Wadekar * Jump to BL31_BASE and start execution again 299939dcf25SVarun Wadekar * ---------------------------------------------------- 300939dcf25SVarun Wadekar */ 301939dcf25SVarun Wadekar_end: mov x0, x20 302939dcf25SVarun Wadekar mov x1, x21 303939dcf25SVarun Wadekar br x17 304939dcf25SVarun Wadekar1: 305939dcf25SVarun Wadekar 30608438e24SVarun Wadekar /* ----------------------------------- 30708438e24SVarun Wadekar * derive and save the phys_base addr 30808438e24SVarun Wadekar * ----------------------------------- 30908438e24SVarun Wadekar */ 31008438e24SVarun Wadekar adr x17, tegra_bl31_phys_base 31108438e24SVarun Wadekar ldr x18, [x17] 31208438e24SVarun Wadekar cbnz x18, 1f 31308438e24SVarun Wadekar adr x18, bl31_entrypoint 31408438e24SVarun Wadekar str x18, [x17] 31508438e24SVarun Wadekar 31608438e24SVarun Wadekar1: cpu_init_common 31708438e24SVarun Wadekar 31808438e24SVarun Wadekar ret 31908438e24SVarun Wadekarendfunc plat_reset_handler 32008438e24SVarun Wadekar 32108438e24SVarun Wadekar /* ---------------------------------------- 32208438e24SVarun Wadekar * Secure entrypoint function for CPU boot 32308438e24SVarun Wadekar * ---------------------------------------- 32408438e24SVarun Wadekar */ 32564726e6dSJulius Wernerfunc tegra_secure_entrypoint _align=6 32608438e24SVarun Wadekar 32708438e24SVarun Wadekar#if ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT 32808438e24SVarun Wadekar 329c195fec6SHarvey Hsieh /* -------------------------------------------------------- 330c195fec6SHarvey Hsieh * Skip the invalidate BTB workaround for Tegra210B01 SKUs. 331c195fec6SHarvey Hsieh * -------------------------------------------------------- 332c195fec6SHarvey Hsieh */ 333c195fec6SHarvey Hsieh mov x0, #TEGRA_MISC_BASE 334c195fec6SHarvey Hsieh add x0, x0, #HARDWARE_REVISION_OFFSET 335c195fec6SHarvey Hsieh ldr w1, [x0] 336c195fec6SHarvey Hsieh lsr w1, w1, #CHIP_ID_SHIFT 337c195fec6SHarvey Hsieh and w1, w1, #CHIP_ID_MASK 338c195fec6SHarvey Hsieh cmp w1, #TEGRA_CHIPID_TEGRA21 /* T210? */ 339c195fec6SHarvey Hsieh b.ne 2f 340c195fec6SHarvey Hsieh ldr w1, [x0] 341c195fec6SHarvey Hsieh lsr w1, w1, #MAJOR_VERSION_SHIFT 342c195fec6SHarvey Hsieh and w1, w1, #MAJOR_VERSION_MASK 343c195fec6SHarvey Hsieh cmp w1, #0x02 /* T210 B01? */ 344c195fec6SHarvey Hsieh b.eq 2f 345c195fec6SHarvey Hsieh 34608438e24SVarun Wadekar /* ------------------------------------------------------- 34708438e24SVarun Wadekar * Invalidate BTB along with I$ to remove any stale 34808438e24SVarun Wadekar * entries from the branch predictor array. 34908438e24SVarun Wadekar * ------------------------------------------------------- 35008438e24SVarun Wadekar */ 351d0e1094eSEleanor Bonnici mrs x0, CORTEX_A57_CPUACTLR_EL1 35208438e24SVarun Wadekar orr x0, x0, #1 353d0e1094eSEleanor Bonnici msr CORTEX_A57_CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */ 35408438e24SVarun Wadekar dsb sy 35508438e24SVarun Wadekar isb 35608438e24SVarun Wadekar ic iallu /* actual invalidate */ 35708438e24SVarun Wadekar dsb sy 35808438e24SVarun Wadekar isb 35908438e24SVarun Wadekar 360d0e1094eSEleanor Bonnici mrs x0, CORTEX_A57_CPUACTLR_EL1 36108438e24SVarun Wadekar bic x0, x0, #1 362d0e1094eSEleanor Bonnici msr CORTEX_A57_CPUACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */ 36308438e24SVarun Wadekar dsb sy 36408438e24SVarun Wadekar isb 36508438e24SVarun Wadekar 36608438e24SVarun Wadekar .rept 7 36708438e24SVarun Wadekar nop /* wait */ 36808438e24SVarun Wadekar .endr 36908438e24SVarun Wadekar 37008438e24SVarun Wadekar /* ----------------------------------------------- 37108438e24SVarun Wadekar * Extract OSLK bit and check if it is '1'. This 37208438e24SVarun Wadekar * bit remains '0' for A53 on warm-resets. If '1', 37308438e24SVarun Wadekar * turn off regional clock gating and request warm 37408438e24SVarun Wadekar * reset. 37508438e24SVarun Wadekar * ----------------------------------------------- 37608438e24SVarun Wadekar */ 37708438e24SVarun Wadekar mrs x0, oslsr_el1 37808438e24SVarun Wadekar and x0, x0, #2 37908438e24SVarun Wadekar mrs x1, mpidr_el1 38008438e24SVarun Wadekar bics xzr, x0, x1, lsr #7 /* 0 = slow cluster or warm reset */ 38108438e24SVarun Wadekar b.eq restore_oslock 38208438e24SVarun Wadekar mov x0, xzr 38308438e24SVarun Wadekar msr oslar_el1, x0 /* os lock stays 0 across warm reset */ 38408438e24SVarun Wadekar mov x3, #3 38508438e24SVarun Wadekar movz x4, #0x8000, lsl #48 386d0e1094eSEleanor Bonnici msr CORTEX_A57_CPUACTLR_EL1, x4 /* turn off RCG */ 38708438e24SVarun Wadekar isb 38808438e24SVarun Wadekar msr rmr_el3, x3 /* request warm reset */ 38908438e24SVarun Wadekar isb 39008438e24SVarun Wadekar dsb sy 39108438e24SVarun Wadekar1: wfi 39208438e24SVarun Wadekar b 1b 39308438e24SVarun Wadekar 39408438e24SVarun Wadekar /* -------------------------------------------------- 39508438e24SVarun Wadekar * These nops are here so that speculative execution 39608438e24SVarun Wadekar * won't harm us before we are done with warm reset. 39708438e24SVarun Wadekar * -------------------------------------------------- 39808438e24SVarun Wadekar */ 39908438e24SVarun Wadekar .rept 65 40008438e24SVarun Wadekar nop 40108438e24SVarun Wadekar .endr 402c195fec6SHarvey Hsieh2: 40308438e24SVarun Wadekar /* -------------------------------------------------- 40408438e24SVarun Wadekar * Do not insert instructions here 40508438e24SVarun Wadekar * -------------------------------------------------- 40608438e24SVarun Wadekar */ 40708438e24SVarun Wadekar#endif 40808438e24SVarun Wadekar 40908438e24SVarun Wadekar /* -------------------------------------------------- 41008438e24SVarun Wadekar * Restore OS Lock bit 41108438e24SVarun Wadekar * -------------------------------------------------- 41208438e24SVarun Wadekar */ 41308438e24SVarun Wadekarrestore_oslock: 41408438e24SVarun Wadekar mov x0, #1 41508438e24SVarun Wadekar msr oslar_el1, x0 41608438e24SVarun Wadekar 41708438e24SVarun Wadekar cpu_init_common 41808438e24SVarun Wadekar 41908438e24SVarun Wadekar /* --------------------------------------------------------------------- 42008438e24SVarun Wadekar * The initial state of the Architectural feature trap register 42108438e24SVarun Wadekar * (CPTR_EL3) is unknown and it must be set to a known state. All 42208438e24SVarun Wadekar * feature traps are disabled. Some bits in this register are marked as 42308438e24SVarun Wadekar * Reserved and should not be modified. 42408438e24SVarun Wadekar * 42508438e24SVarun Wadekar * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1 42608438e24SVarun Wadekar * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2. 42708438e24SVarun Wadekar * CPTR_EL3.TTA: This causes access to the Trace functionality to trap 42808438e24SVarun Wadekar * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register 42908438e24SVarun Wadekar * access to trace functionality is not supported, this bit is RES0. 43008438e24SVarun Wadekar * CPTR_EL3.TFP: This causes instructions that access the registers 43108438e24SVarun Wadekar * associated with Floating Point and Advanced SIMD execution to trap 43208438e24SVarun Wadekar * to EL3 when executed from any exception level, unless trapped to EL1 43308438e24SVarun Wadekar * or EL2. 43408438e24SVarun Wadekar * --------------------------------------------------------------------- 43508438e24SVarun Wadekar */ 43608438e24SVarun Wadekar mrs x1, cptr_el3 43708438e24SVarun Wadekar bic w1, w1, #TCPAC_BIT 43808438e24SVarun Wadekar bic w1, w1, #TTA_BIT 43908438e24SVarun Wadekar bic w1, w1, #TFP_BIT 44008438e24SVarun Wadekar msr cptr_el3, x1 44108438e24SVarun Wadekar 44208438e24SVarun Wadekar /* -------------------------------------------------- 44308438e24SVarun Wadekar * Get secure world's entry point and jump to it 44408438e24SVarun Wadekar * -------------------------------------------------- 44508438e24SVarun Wadekar */ 44671cb26eaSVarun Wadekar bl plat_get_my_entrypoint 44708438e24SVarun Wadekar br x0 44808438e24SVarun Wadekarendfunc tegra_secure_entrypoint 44908438e24SVarun Wadekar 45008438e24SVarun Wadekar .data 45108438e24SVarun Wadekar .align 3 45208438e24SVarun Wadekar 45308438e24SVarun Wadekar /* -------------------------------------------------- 45471cb26eaSVarun Wadekar * CPU Secure entry point - resume from suspend 45508438e24SVarun Wadekar * -------------------------------------------------- 45608438e24SVarun Wadekar */ 45771cb26eaSVarun Wadekartegra_sec_entry_point: 45808438e24SVarun Wadekar .quad 0 45908438e24SVarun Wadekar 46008438e24SVarun Wadekar /* -------------------------------------------------- 46108438e24SVarun Wadekar * NS world's cold boot entry point 46208438e24SVarun Wadekar * -------------------------------------------------- 46308438e24SVarun Wadekar */ 46408438e24SVarun Wadekarns_image_entrypoint: 46508438e24SVarun Wadekar .quad 0 46608438e24SVarun Wadekar 46708438e24SVarun Wadekar /* -------------------------------------------------- 46808438e24SVarun Wadekar * BL31's physical base address 46908438e24SVarun Wadekar * -------------------------------------------------- 47008438e24SVarun Wadekar */ 47108438e24SVarun Wadekartegra_bl31_phys_base: 47208438e24SVarun Wadekar .quad 0 473e1084216SVarun Wadekar 474e1084216SVarun Wadekar /* -------------------------------------------------- 475e1084216SVarun Wadekar * UART controller base for console init 476e1084216SVarun Wadekar * -------------------------------------------------- 477e1084216SVarun Wadekar */ 478e1084216SVarun Wadekartegra_console_base: 479e1084216SVarun Wadekar .quad 0 480