108438e24SVarun Wadekar/* 2*544c092bSAmbroise Vincent * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 508438e24SVarun Wadekar */ 608438e24SVarun Wadekar#include <arch.h> 708438e24SVarun Wadekar#include <asm_macros.S> 808438e24SVarun Wadekar#include <assert_macros.S> 908438e24SVarun Wadekar#include <cpu_macros.S> 1008438e24SVarun Wadekar#include <cortex_a53.h> 11ee1ebbd1SIsla Mitchell#include <cortex_a57.h> 1211bd24beSVarun Wadekar#include <platform_def.h> 1308438e24SVarun Wadekar#include <tegra_def.h> 14c195fec6SHarvey Hsieh#include <tegra_platform.h> 1508438e24SVarun Wadekar 160cd6138dSVarun Wadekar#define MIDR_PN_CORTEX_A57 0xD07 170cd6138dSVarun Wadekar 180cd6138dSVarun Wadekar/******************************************************************************* 190cd6138dSVarun Wadekar * Implementation defined ACTLR_EL3 bit definitions 200cd6138dSVarun Wadekar ******************************************************************************/ 2175516c3eSSteven Kao#define ACTLR_EL3_L2ACTLR_BIT (U(1) << 6) 2275516c3eSSteven Kao#define ACTLR_EL3_L2ECTLR_BIT (U(1) << 5) 2375516c3eSSteven Kao#define ACTLR_EL3_L2CTLR_BIT (U(1) << 4) 2475516c3eSSteven Kao#define ACTLR_EL3_CPUECTLR_BIT (U(1) << 1) 2575516c3eSSteven Kao#define ACTLR_EL3_CPUACTLR_BIT (U(1) << 0) 2675516c3eSSteven Kao#define ACTLR_EL3_ENABLE_ALL_MASK (ACTLR_EL3_L2ACTLR_BIT | \ 2775516c3eSSteven Kao ACTLR_EL3_L2ECTLR_BIT | \ 2875516c3eSSteven Kao ACTLR_EL3_L2CTLR_BIT | \ 2975516c3eSSteven Kao ACTLR_EL3_CPUECTLR_BIT | \ 3075516c3eSSteven Kao ACTLR_EL3_CPUACTLR_BIT) 310cd6138dSVarun Wadekar#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ 320cd6138dSVarun Wadekar ACTLR_EL3_L2ECTLR_BIT | \ 330cd6138dSVarun Wadekar ACTLR_EL3_L2CTLR_BIT | \ 340cd6138dSVarun Wadekar ACTLR_EL3_CPUECTLR_BIT | \ 350cd6138dSVarun Wadekar ACTLR_EL3_CPUACTLR_BIT) 360cd6138dSVarun Wadekar 3708438e24SVarun Wadekar /* Global functions */ 3871cb26eaSVarun Wadekar .globl plat_is_my_cpu_primary 3971cb26eaSVarun Wadekar .globl plat_my_core_pos 4071cb26eaSVarun Wadekar .globl plat_get_my_entrypoint 4108438e24SVarun Wadekar .globl plat_secondary_cold_boot_setup 4208438e24SVarun Wadekar .globl platform_mem_init 4308438e24SVarun Wadekar .globl plat_crash_console_init 4408438e24SVarun Wadekar .globl plat_crash_console_putc 459c675b37SAntonio Nino Diaz .globl plat_crash_console_flush 4608438e24SVarun Wadekar .globl tegra_secure_entrypoint 4708438e24SVarun Wadekar .globl plat_reset_handler 4808438e24SVarun Wadekar 4908438e24SVarun Wadekar /* Global variables */ 5071cb26eaSVarun Wadekar .globl tegra_sec_entry_point 5108438e24SVarun Wadekar .globl ns_image_entrypoint 5208438e24SVarun Wadekar .globl tegra_bl31_phys_base 53e1084216SVarun Wadekar .globl tegra_console_base 5408438e24SVarun Wadekar 5508438e24SVarun Wadekar /* --------------------- 5608438e24SVarun Wadekar * Common CPU init code 5708438e24SVarun Wadekar * --------------------- 5808438e24SVarun Wadekar */ 5908438e24SVarun Wadekar.macro cpu_init_common 6008438e24SVarun Wadekar 610cd6138dSVarun Wadekar /* ------------------------------------------------ 62018b8480SVarun Wadekar * We enable procesor retention, L2/CPUECTLR NS 63018b8480SVarun Wadekar * access and ECC/Parity protection for A57 CPUs 640cd6138dSVarun Wadekar * ------------------------------------------------ 650cd6138dSVarun Wadekar */ 660cd6138dSVarun Wadekar mrs x0, midr_el1 670cd6138dSVarun Wadekar mov x1, #(MIDR_PN_MASK << MIDR_PN_SHIFT) 680cd6138dSVarun Wadekar and x0, x0, x1 690cd6138dSVarun Wadekar lsr x0, x0, #MIDR_PN_SHIFT 700cd6138dSVarun Wadekar cmp x0, #MIDR_PN_CORTEX_A57 710cd6138dSVarun Wadekar b.ne 1f 720cd6138dSVarun Wadekar 73b42192bcSVarun Wadekar /* --------------------------- 74b42192bcSVarun Wadekar * Enable processor retention 75b42192bcSVarun Wadekar * --------------------------- 76b42192bcSVarun Wadekar */ 77fb7d32e5SVarun Wadekar mrs x0, CORTEX_A57_L2ECTLR_EL1 78fb7d32e5SVarun Wadekar mov x1, #RETENTION_ENTRY_TICKS_512 79fb7d32e5SVarun Wadekar bic x0, x0, #CORTEX_A57_L2ECTLR_RET_CTRL_MASK 80b42192bcSVarun Wadekar orr x0, x0, x1 81fb7d32e5SVarun Wadekar msr CORTEX_A57_L2ECTLR_EL1, x0 82b42192bcSVarun Wadekar isb 83b42192bcSVarun Wadekar 84fb7d32e5SVarun Wadekar mrs x0, CORTEX_A57_ECTLR_EL1 85fb7d32e5SVarun Wadekar mov x1, #RETENTION_ENTRY_TICKS_512 86fb7d32e5SVarun Wadekar bic x0, x0, #CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK 87b42192bcSVarun Wadekar orr x0, x0, x1 88fb7d32e5SVarun Wadekar msr CORTEX_A57_ECTLR_EL1, x0 89b42192bcSVarun Wadekar isb 90b42192bcSVarun Wadekar 9108438e24SVarun Wadekar /* ------------------------------------------------------- 9208438e24SVarun Wadekar * Enable L2 and CPU ECTLR RW access from non-secure world 9308438e24SVarun Wadekar * ------------------------------------------------------- 9408438e24SVarun Wadekar */ 9575516c3eSSteven Kao mrs x0, actlr_el3 9675516c3eSSteven Kao mov x1, #ACTLR_EL3_ENABLE_ALL_MASK 9775516c3eSSteven Kao bic x0, x0, x1 9875516c3eSSteven Kao mov x1, #ACTLR_EL3_ENABLE_ALL_ACCESS 9975516c3eSSteven Kao orr x0, x0, x1 10008438e24SVarun Wadekar msr actlr_el3, x0 10175516c3eSSteven Kao mrs x0, actlr_el2 10275516c3eSSteven Kao mov x1, #ACTLR_EL3_ENABLE_ALL_MASK 10375516c3eSSteven Kao bic x0, x0, x1 10475516c3eSSteven Kao mov x1, #ACTLR_EL3_ENABLE_ALL_ACCESS 10575516c3eSSteven Kao orr x0, x0, x1 10608438e24SVarun Wadekar msr actlr_el2, x0 10708438e24SVarun Wadekar isb 10808438e24SVarun Wadekar 10908438e24SVarun Wadekar /* -------------------------------- 11008438e24SVarun Wadekar * Enable the cycle count register 11108438e24SVarun Wadekar * -------------------------------- 11208438e24SVarun Wadekar */ 1130cd6138dSVarun Wadekar1: mrs x0, pmcr_el0 11408438e24SVarun Wadekar ubfx x0, x0, #11, #5 // read PMCR.N field 11508438e24SVarun Wadekar mov x1, #1 11608438e24SVarun Wadekar lsl x0, x1, x0 11708438e24SVarun Wadekar sub x0, x0, #1 // mask of event counters 11808438e24SVarun Wadekar orr x0, x0, #0x80000000 // disable overflow intrs 11908438e24SVarun Wadekar msr pmintenclr_el1, x0 12008438e24SVarun Wadekar msr pmuserenr_el0, x1 // enable user mode access 12108438e24SVarun Wadekar 12208438e24SVarun Wadekar /* ---------------------------------------------------------------- 12308438e24SVarun Wadekar * Allow non-privileged access to CNTVCT: Set CNTKCTL (Kernel Count 12408438e24SVarun Wadekar * register), bit 1 (EL0VCTEN) to enable access to CNTVCT/CNTFRQ 12508438e24SVarun Wadekar * registers from EL0. 12608438e24SVarun Wadekar * ---------------------------------------------------------------- 12708438e24SVarun Wadekar */ 12808438e24SVarun Wadekar mrs x0, cntkctl_el1 12908438e24SVarun Wadekar orr x0, x0, #EL0VCTEN_BIT 13008438e24SVarun Wadekar msr cntkctl_el1, x0 13108438e24SVarun Wadekar.endm 13208438e24SVarun Wadekar 13308438e24SVarun Wadekar /* ----------------------------------------------------- 13471cb26eaSVarun Wadekar * unsigned int plat_is_my_cpu_primary(void); 13508438e24SVarun Wadekar * 13608438e24SVarun Wadekar * This function checks if this is the Primary CPU 13708438e24SVarun Wadekar * ----------------------------------------------------- 13808438e24SVarun Wadekar */ 13971cb26eaSVarun Wadekarfunc plat_is_my_cpu_primary 14071cb26eaSVarun Wadekar mrs x0, mpidr_el1 14108438e24SVarun Wadekar and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 14208438e24SVarun Wadekar cmp x0, #TEGRA_PRIMARY_CPU 14308438e24SVarun Wadekar cset x0, eq 14408438e24SVarun Wadekar ret 14571cb26eaSVarun Wadekarendfunc plat_is_my_cpu_primary 14608438e24SVarun Wadekar 147b627d083SVarun Wadekar /* ---------------------------------------------------------- 14871cb26eaSVarun Wadekar * unsigned int plat_my_core_pos(void); 14908438e24SVarun Wadekar * 150b627d083SVarun Wadekar * result: CorePos = CoreId + (ClusterId * cpus per cluster) 151b627d083SVarun Wadekar * ---------------------------------------------------------- 15208438e24SVarun Wadekar */ 15371cb26eaSVarun Wadekarfunc plat_my_core_pos 15471cb26eaSVarun Wadekar mrs x0, mpidr_el1 15571cb26eaSVarun Wadekar and x1, x0, #MPIDR_CPU_MASK 15671cb26eaSVarun Wadekar and x0, x0, #MPIDR_CLUSTER_MASK 157b627d083SVarun Wadekar lsr x0, x0, #MPIDR_AFFINITY_BITS 158b627d083SVarun Wadekar mov x2, #PLATFORM_MAX_CPUS_PER_CLUSTER 159b627d083SVarun Wadekar mul x0, x0, x2 160b627d083SVarun Wadekar add x0, x1, x0 16108438e24SVarun Wadekar ret 16271cb26eaSVarun Wadekarendfunc plat_my_core_pos 16371cb26eaSVarun Wadekar 16471cb26eaSVarun Wadekar /* ----------------------------------------------------- 16571cb26eaSVarun Wadekar * unsigned long plat_get_my_entrypoint (void); 16671cb26eaSVarun Wadekar * 16771cb26eaSVarun Wadekar * Main job of this routine is to distinguish between 16871cb26eaSVarun Wadekar * a cold and warm boot. If the tegra_sec_entry_point for 16971cb26eaSVarun Wadekar * this CPU is present, then it's a warm boot. 17071cb26eaSVarun Wadekar * 17171cb26eaSVarun Wadekar * ----------------------------------------------------- 17271cb26eaSVarun Wadekar */ 17371cb26eaSVarun Wadekarfunc plat_get_my_entrypoint 17471cb26eaSVarun Wadekar adr x1, tegra_sec_entry_point 17571cb26eaSVarun Wadekar ldr x0, [x1] 17671cb26eaSVarun Wadekar ret 17771cb26eaSVarun Wadekarendfunc plat_get_my_entrypoint 17808438e24SVarun Wadekar 17908438e24SVarun Wadekar /* ----------------------------------------------------- 180bde81dccSVarun Wadekar * int platform_get_core_pos(int mpidr); 181bde81dccSVarun Wadekar * 182b627d083SVarun Wadekar * result: CorePos = (ClusterId * cpus per cluster) + 183bde81dccSVarun Wadekar * CoreId 184bde81dccSVarun Wadekar * ----------------------------------------------------- 185bde81dccSVarun Wadekar */ 186bde81dccSVarun Wadekarfunc platform_get_core_pos 187bde81dccSVarun Wadekar and x1, x0, #MPIDR_CPU_MASK 188bde81dccSVarun Wadekar and x0, x0, #MPIDR_CLUSTER_MASK 189b627d083SVarun Wadekar lsr x0, x0, #MPIDR_AFFINITY_BITS 190b627d083SVarun Wadekar mov x2, #PLATFORM_MAX_CPUS_PER_CLUSTER 191b627d083SVarun Wadekar mul x0, x0, x2 192b627d083SVarun Wadekar add x0, x1, x0 193bde81dccSVarun Wadekar ret 194bde81dccSVarun Wadekarendfunc platform_get_core_pos 195bde81dccSVarun Wadekar 196bde81dccSVarun Wadekar /* ----------------------------------------------------- 19708438e24SVarun Wadekar * void plat_secondary_cold_boot_setup (void); 19808438e24SVarun Wadekar * 19908438e24SVarun Wadekar * This function performs any platform specific actions 20008438e24SVarun Wadekar * needed for a secondary cpu after a cold reset. Right 20108438e24SVarun Wadekar * now this is a stub function. 20208438e24SVarun Wadekar * ----------------------------------------------------- 20308438e24SVarun Wadekar */ 20408438e24SVarun Wadekarfunc plat_secondary_cold_boot_setup 20508438e24SVarun Wadekar mov x0, #0 20608438e24SVarun Wadekar ret 20708438e24SVarun Wadekarendfunc plat_secondary_cold_boot_setup 20808438e24SVarun Wadekar 20908438e24SVarun Wadekar /* -------------------------------------------------------- 21008438e24SVarun Wadekar * void platform_mem_init (void); 21108438e24SVarun Wadekar * 21208438e24SVarun Wadekar * Any memory init, relocation to be done before the 21308438e24SVarun Wadekar * platform boots. Called very early in the boot process. 21408438e24SVarun Wadekar * -------------------------------------------------------- 21508438e24SVarun Wadekar */ 21608438e24SVarun Wadekarfunc platform_mem_init 21708438e24SVarun Wadekar mov x0, #0 21808438e24SVarun Wadekar ret 21908438e24SVarun Wadekarendfunc platform_mem_init 22008438e24SVarun Wadekar 22108438e24SVarun Wadekar /* --------------------------------------------------- 22208438e24SVarun Wadekar * Function to handle a platform reset and store 22308438e24SVarun Wadekar * input parameters passed by BL2. 22408438e24SVarun Wadekar * --------------------------------------------------- 22508438e24SVarun Wadekar */ 22608438e24SVarun Wadekarfunc plat_reset_handler 22708438e24SVarun Wadekar 228939dcf25SVarun Wadekar /* ---------------------------------------------------- 229939dcf25SVarun Wadekar * Verify if we are running from BL31_BASE address 230939dcf25SVarun Wadekar * ---------------------------------------------------- 231939dcf25SVarun Wadekar */ 232939dcf25SVarun Wadekar adr x18, bl31_entrypoint 233939dcf25SVarun Wadekar mov x17, #BL31_BASE 234939dcf25SVarun Wadekar cmp x18, x17 235939dcf25SVarun Wadekar b.eq 1f 236939dcf25SVarun Wadekar 237939dcf25SVarun Wadekar /* ---------------------------------------------------- 238939dcf25SVarun Wadekar * Copy the entire BL31 code to BL31_BASE if we are not 239939dcf25SVarun Wadekar * running from it already 240939dcf25SVarun Wadekar * ---------------------------------------------------- 241939dcf25SVarun Wadekar */ 242939dcf25SVarun Wadekar mov x0, x17 243939dcf25SVarun Wadekar mov x1, x18 244939dcf25SVarun Wadekar mov x2, #BL31_SIZE 245939dcf25SVarun Wadekar_loop16: 246939dcf25SVarun Wadekar cmp x2, #16 247768baf6eSDouglas Raillard b.lo _loop1 248939dcf25SVarun Wadekar ldp x3, x4, [x1], #16 249939dcf25SVarun Wadekar stp x3, x4, [x0], #16 250939dcf25SVarun Wadekar sub x2, x2, #16 251939dcf25SVarun Wadekar b _loop16 252939dcf25SVarun Wadekar /* copy byte per byte */ 253939dcf25SVarun Wadekar_loop1: 254939dcf25SVarun Wadekar cbz x2, _end 255939dcf25SVarun Wadekar ldrb w3, [x1], #1 256939dcf25SVarun Wadekar strb w3, [x0], #1 257939dcf25SVarun Wadekar subs x2, x2, #1 258939dcf25SVarun Wadekar b.ne _loop1 259939dcf25SVarun Wadekar 260939dcf25SVarun Wadekar /* ---------------------------------------------------- 261939dcf25SVarun Wadekar * Jump to BL31_BASE and start execution again 262939dcf25SVarun Wadekar * ---------------------------------------------------- 263939dcf25SVarun Wadekar */ 264939dcf25SVarun Wadekar_end: mov x0, x20 265939dcf25SVarun Wadekar mov x1, x21 266939dcf25SVarun Wadekar br x17 267939dcf25SVarun Wadekar1: 268939dcf25SVarun Wadekar 26908438e24SVarun Wadekar /* ----------------------------------- 27008438e24SVarun Wadekar * derive and save the phys_base addr 27108438e24SVarun Wadekar * ----------------------------------- 27208438e24SVarun Wadekar */ 27308438e24SVarun Wadekar adr x17, tegra_bl31_phys_base 27408438e24SVarun Wadekar ldr x18, [x17] 27508438e24SVarun Wadekar cbnz x18, 1f 27608438e24SVarun Wadekar adr x18, bl31_entrypoint 27708438e24SVarun Wadekar str x18, [x17] 27808438e24SVarun Wadekar 27908438e24SVarun Wadekar1: cpu_init_common 28008438e24SVarun Wadekar 28108438e24SVarun Wadekar ret 28208438e24SVarun Wadekarendfunc plat_reset_handler 28308438e24SVarun Wadekar 28408438e24SVarun Wadekar /* ---------------------------------------- 28508438e24SVarun Wadekar * Secure entrypoint function for CPU boot 28608438e24SVarun Wadekar * ---------------------------------------- 28708438e24SVarun Wadekar */ 28864726e6dSJulius Wernerfunc tegra_secure_entrypoint _align=6 28908438e24SVarun Wadekar 29008438e24SVarun Wadekar#if ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT 29108438e24SVarun Wadekar 292c195fec6SHarvey Hsieh /* -------------------------------------------------------- 293c195fec6SHarvey Hsieh * Skip the invalidate BTB workaround for Tegra210B01 SKUs. 294c195fec6SHarvey Hsieh * -------------------------------------------------------- 295c195fec6SHarvey Hsieh */ 296c195fec6SHarvey Hsieh mov x0, #TEGRA_MISC_BASE 297c195fec6SHarvey Hsieh add x0, x0, #HARDWARE_REVISION_OFFSET 298c195fec6SHarvey Hsieh ldr w1, [x0] 299c195fec6SHarvey Hsieh lsr w1, w1, #CHIP_ID_SHIFT 300c195fec6SHarvey Hsieh and w1, w1, #CHIP_ID_MASK 301c195fec6SHarvey Hsieh cmp w1, #TEGRA_CHIPID_TEGRA21 /* T210? */ 302c195fec6SHarvey Hsieh b.ne 2f 303c195fec6SHarvey Hsieh ldr w1, [x0] 304c195fec6SHarvey Hsieh lsr w1, w1, #MAJOR_VERSION_SHIFT 305c195fec6SHarvey Hsieh and w1, w1, #MAJOR_VERSION_MASK 306c195fec6SHarvey Hsieh cmp w1, #0x02 /* T210 B01? */ 307c195fec6SHarvey Hsieh b.eq 2f 308c195fec6SHarvey Hsieh 30908438e24SVarun Wadekar /* ------------------------------------------------------- 31008438e24SVarun Wadekar * Invalidate BTB along with I$ to remove any stale 31108438e24SVarun Wadekar * entries from the branch predictor array. 31208438e24SVarun Wadekar * ------------------------------------------------------- 31308438e24SVarun Wadekar */ 314d0e1094eSEleanor Bonnici mrs x0, CORTEX_A57_CPUACTLR_EL1 31508438e24SVarun Wadekar orr x0, x0, #1 316d0e1094eSEleanor Bonnici msr CORTEX_A57_CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */ 31708438e24SVarun Wadekar dsb sy 31808438e24SVarun Wadekar isb 31908438e24SVarun Wadekar ic iallu /* actual invalidate */ 32008438e24SVarun Wadekar dsb sy 32108438e24SVarun Wadekar isb 32208438e24SVarun Wadekar 323d0e1094eSEleanor Bonnici mrs x0, CORTEX_A57_CPUACTLR_EL1 32408438e24SVarun Wadekar bic x0, x0, #1 325d0e1094eSEleanor Bonnici msr CORTEX_A57_CPUACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */ 32608438e24SVarun Wadekar dsb sy 32708438e24SVarun Wadekar isb 32808438e24SVarun Wadekar 32908438e24SVarun Wadekar .rept 7 33008438e24SVarun Wadekar nop /* wait */ 33108438e24SVarun Wadekar .endr 33208438e24SVarun Wadekar 33308438e24SVarun Wadekar /* ----------------------------------------------- 33408438e24SVarun Wadekar * Extract OSLK bit and check if it is '1'. This 33508438e24SVarun Wadekar * bit remains '0' for A53 on warm-resets. If '1', 33608438e24SVarun Wadekar * turn off regional clock gating and request warm 33708438e24SVarun Wadekar * reset. 33808438e24SVarun Wadekar * ----------------------------------------------- 33908438e24SVarun Wadekar */ 34008438e24SVarun Wadekar mrs x0, oslsr_el1 34108438e24SVarun Wadekar and x0, x0, #2 34208438e24SVarun Wadekar mrs x1, mpidr_el1 34308438e24SVarun Wadekar bics xzr, x0, x1, lsr #7 /* 0 = slow cluster or warm reset */ 34408438e24SVarun Wadekar b.eq restore_oslock 34508438e24SVarun Wadekar mov x0, xzr 34608438e24SVarun Wadekar msr oslar_el1, x0 /* os lock stays 0 across warm reset */ 34708438e24SVarun Wadekar mov x3, #3 34808438e24SVarun Wadekar movz x4, #0x8000, lsl #48 349d0e1094eSEleanor Bonnici msr CORTEX_A57_CPUACTLR_EL1, x4 /* turn off RCG */ 35008438e24SVarun Wadekar isb 35108438e24SVarun Wadekar msr rmr_el3, x3 /* request warm reset */ 35208438e24SVarun Wadekar isb 35308438e24SVarun Wadekar dsb sy 35408438e24SVarun Wadekar1: wfi 35508438e24SVarun Wadekar b 1b 35608438e24SVarun Wadekar 35708438e24SVarun Wadekar /* -------------------------------------------------- 35808438e24SVarun Wadekar * These nops are here so that speculative execution 35908438e24SVarun Wadekar * won't harm us before we are done with warm reset. 36008438e24SVarun Wadekar * -------------------------------------------------- 36108438e24SVarun Wadekar */ 36208438e24SVarun Wadekar .rept 65 36308438e24SVarun Wadekar nop 36408438e24SVarun Wadekar .endr 365c195fec6SHarvey Hsieh2: 36608438e24SVarun Wadekar /* -------------------------------------------------- 36708438e24SVarun Wadekar * Do not insert instructions here 36808438e24SVarun Wadekar * -------------------------------------------------- 36908438e24SVarun Wadekar */ 37008438e24SVarun Wadekar#endif 37108438e24SVarun Wadekar 37208438e24SVarun Wadekar /* -------------------------------------------------- 37308438e24SVarun Wadekar * Restore OS Lock bit 37408438e24SVarun Wadekar * -------------------------------------------------- 37508438e24SVarun Wadekar */ 37608438e24SVarun Wadekarrestore_oslock: 37708438e24SVarun Wadekar mov x0, #1 37808438e24SVarun Wadekar msr oslar_el1, x0 37908438e24SVarun Wadekar 38008438e24SVarun Wadekar /* -------------------------------------------------- 38108438e24SVarun Wadekar * Get secure world's entry point and jump to it 38208438e24SVarun Wadekar * -------------------------------------------------- 38308438e24SVarun Wadekar */ 38471cb26eaSVarun Wadekar bl plat_get_my_entrypoint 38508438e24SVarun Wadekar br x0 38608438e24SVarun Wadekarendfunc tegra_secure_entrypoint 38708438e24SVarun Wadekar 38808438e24SVarun Wadekar .data 38908438e24SVarun Wadekar .align 3 39008438e24SVarun Wadekar 39108438e24SVarun Wadekar /* -------------------------------------------------- 39271cb26eaSVarun Wadekar * CPU Secure entry point - resume from suspend 39308438e24SVarun Wadekar * -------------------------------------------------- 39408438e24SVarun Wadekar */ 39571cb26eaSVarun Wadekartegra_sec_entry_point: 39608438e24SVarun Wadekar .quad 0 39708438e24SVarun Wadekar 39808438e24SVarun Wadekar /* -------------------------------------------------- 39908438e24SVarun Wadekar * NS world's cold boot entry point 40008438e24SVarun Wadekar * -------------------------------------------------- 40108438e24SVarun Wadekar */ 40208438e24SVarun Wadekarns_image_entrypoint: 40308438e24SVarun Wadekar .quad 0 40408438e24SVarun Wadekar 40508438e24SVarun Wadekar /* -------------------------------------------------- 40608438e24SVarun Wadekar * BL31's physical base address 40708438e24SVarun Wadekar * -------------------------------------------------- 40808438e24SVarun Wadekar */ 40908438e24SVarun Wadekartegra_bl31_phys_base: 41008438e24SVarun Wadekar .quad 0 411e1084216SVarun Wadekar 412e1084216SVarun Wadekar /* -------------------------------------------------- 413e1084216SVarun Wadekar * UART controller base for console init 414e1084216SVarun Wadekar * -------------------------------------------------- 415e1084216SVarun Wadekar */ 416e1084216SVarun Wadekartegra_console_base: 417e1084216SVarun Wadekar .quad 0 418