108438e24SVarun Wadekar/* 2544c092bSAmbroise Vincent * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3b1481cffSVarun Wadekar * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 408438e24SVarun Wadekar * 582cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 608438e24SVarun Wadekar */ 708438e24SVarun Wadekar#include <arch.h> 808438e24SVarun Wadekar#include <asm_macros.S> 908438e24SVarun Wadekar#include <assert_macros.S> 1008438e24SVarun Wadekar#include <cpu_macros.S> 1108438e24SVarun Wadekar#include <cortex_a53.h> 12ee1ebbd1SIsla Mitchell#include <cortex_a57.h> 1311bd24beSVarun Wadekar#include <platform_def.h> 1408438e24SVarun Wadekar#include <tegra_def.h> 15c195fec6SHarvey Hsieh#include <tegra_platform.h> 1608438e24SVarun Wadekar 170cd6138dSVarun Wadekar#define MIDR_PN_CORTEX_A57 0xD07 180cd6138dSVarun Wadekar 190cd6138dSVarun Wadekar/******************************************************************************* 200cd6138dSVarun Wadekar * Implementation defined ACTLR_EL3 bit definitions 210cd6138dSVarun Wadekar ******************************************************************************/ 22b1481cffSVarun Wadekar#define ACTLR_ELx_L2ACTLR_BIT (U(1) << 6) 23b1481cffSVarun Wadekar#define ACTLR_ELx_L2ECTLR_BIT (U(1) << 5) 24b1481cffSVarun Wadekar#define ACTLR_ELx_L2CTLR_BIT (U(1) << 4) 25b1481cffSVarun Wadekar#define ACTLR_ELx_CPUECTLR_BIT (U(1) << 1) 26b1481cffSVarun Wadekar#define ACTLR_ELx_CPUACTLR_BIT (U(1) << 0) 27b1481cffSVarun Wadekar#define ACTLR_ELx_ENABLE_ALL_ACCESS (ACTLR_ELx_L2ACTLR_BIT | \ 28b1481cffSVarun Wadekar ACTLR_ELx_L2ECTLR_BIT | \ 29b1481cffSVarun Wadekar ACTLR_ELx_L2CTLR_BIT | \ 30b1481cffSVarun Wadekar ACTLR_ELx_CPUECTLR_BIT | \ 31b1481cffSVarun Wadekar ACTLR_ELx_CPUACTLR_BIT) 320cd6138dSVarun Wadekar 3308438e24SVarun Wadekar /* Global functions */ 3471cb26eaSVarun Wadekar .globl plat_is_my_cpu_primary 3571cb26eaSVarun Wadekar .globl plat_my_core_pos 3671cb26eaSVarun Wadekar .globl plat_get_my_entrypoint 3708438e24SVarun Wadekar .globl plat_secondary_cold_boot_setup 3808438e24SVarun Wadekar .globl platform_mem_init 3908438e24SVarun Wadekar .globl plat_crash_console_init 4008438e24SVarun Wadekar .globl plat_crash_console_putc 419c675b37SAntonio Nino Diaz .globl plat_crash_console_flush 42*0ac1bf72SVarun Wadekar .weak plat_core_pos_by_mpidr 4308438e24SVarun Wadekar .globl tegra_secure_entrypoint 4408438e24SVarun Wadekar .globl plat_reset_handler 4508438e24SVarun Wadekar 4608438e24SVarun Wadekar /* Global variables */ 4771cb26eaSVarun Wadekar .globl tegra_sec_entry_point 4808438e24SVarun Wadekar .globl ns_image_entrypoint 4908438e24SVarun Wadekar .globl tegra_bl31_phys_base 50e1084216SVarun Wadekar .globl tegra_console_base 5108438e24SVarun Wadekar 5208438e24SVarun Wadekar /* --------------------- 5308438e24SVarun Wadekar * Common CPU init code 5408438e24SVarun Wadekar * --------------------- 5508438e24SVarun Wadekar */ 5608438e24SVarun Wadekar.macro cpu_init_common 5708438e24SVarun Wadekar 580cd6138dSVarun Wadekar /* ------------------------------------------------ 59018b8480SVarun Wadekar * We enable procesor retention, L2/CPUECTLR NS 60018b8480SVarun Wadekar * access and ECC/Parity protection for A57 CPUs 610cd6138dSVarun Wadekar * ------------------------------------------------ 620cd6138dSVarun Wadekar */ 630cd6138dSVarun Wadekar mrs x0, midr_el1 640cd6138dSVarun Wadekar mov x1, #(MIDR_PN_MASK << MIDR_PN_SHIFT) 650cd6138dSVarun Wadekar and x0, x0, x1 660cd6138dSVarun Wadekar lsr x0, x0, #MIDR_PN_SHIFT 670cd6138dSVarun Wadekar cmp x0, #MIDR_PN_CORTEX_A57 680cd6138dSVarun Wadekar b.ne 1f 690cd6138dSVarun Wadekar 70b42192bcSVarun Wadekar /* --------------------------- 71b42192bcSVarun Wadekar * Enable processor retention 72b42192bcSVarun Wadekar * --------------------------- 73b42192bcSVarun Wadekar */ 74fb7d32e5SVarun Wadekar mrs x0, CORTEX_A57_L2ECTLR_EL1 75fb7d32e5SVarun Wadekar mov x1, #RETENTION_ENTRY_TICKS_512 76fb7d32e5SVarun Wadekar bic x0, x0, #CORTEX_A57_L2ECTLR_RET_CTRL_MASK 77b42192bcSVarun Wadekar orr x0, x0, x1 78fb7d32e5SVarun Wadekar msr CORTEX_A57_L2ECTLR_EL1, x0 79b42192bcSVarun Wadekar isb 80b42192bcSVarun Wadekar 81fb7d32e5SVarun Wadekar mrs x0, CORTEX_A57_ECTLR_EL1 82fb7d32e5SVarun Wadekar mov x1, #RETENTION_ENTRY_TICKS_512 83fb7d32e5SVarun Wadekar bic x0, x0, #CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK 84b42192bcSVarun Wadekar orr x0, x0, x1 85fb7d32e5SVarun Wadekar msr CORTEX_A57_ECTLR_EL1, x0 86b42192bcSVarun Wadekar isb 87b42192bcSVarun Wadekar 8808438e24SVarun Wadekar /* ------------------------------------------------------- 8908438e24SVarun Wadekar * Enable L2 and CPU ECTLR RW access from non-secure world 9008438e24SVarun Wadekar * ------------------------------------------------------- 9108438e24SVarun Wadekar */ 9275516c3eSSteven Kao mrs x0, actlr_el3 93b1481cffSVarun Wadekar mov x1, #ACTLR_ELx_ENABLE_ALL_ACCESS 9475516c3eSSteven Kao orr x0, x0, x1 9508438e24SVarun Wadekar msr actlr_el3, x0 9675516c3eSSteven Kao mrs x0, actlr_el2 97b1481cffSVarun Wadekar mov x1, #ACTLR_ELx_ENABLE_ALL_ACCESS 9875516c3eSSteven Kao orr x0, x0, x1 9908438e24SVarun Wadekar msr actlr_el2, x0 10008438e24SVarun Wadekar isb 10108438e24SVarun Wadekar 10208438e24SVarun Wadekar /* -------------------------------- 10308438e24SVarun Wadekar * Enable the cycle count register 10408438e24SVarun Wadekar * -------------------------------- 10508438e24SVarun Wadekar */ 1060cd6138dSVarun Wadekar1: mrs x0, pmcr_el0 10708438e24SVarun Wadekar ubfx x0, x0, #11, #5 // read PMCR.N field 10808438e24SVarun Wadekar mov x1, #1 10908438e24SVarun Wadekar lsl x0, x1, x0 11008438e24SVarun Wadekar sub x0, x0, #1 // mask of event counters 11108438e24SVarun Wadekar orr x0, x0, #0x80000000 // disable overflow intrs 11208438e24SVarun Wadekar msr pmintenclr_el1, x0 11308438e24SVarun Wadekar msr pmuserenr_el0, x1 // enable user mode access 11408438e24SVarun Wadekar 11508438e24SVarun Wadekar /* ---------------------------------------------------------------- 11608438e24SVarun Wadekar * Allow non-privileged access to CNTVCT: Set CNTKCTL (Kernel Count 11708438e24SVarun Wadekar * register), bit 1 (EL0VCTEN) to enable access to CNTVCT/CNTFRQ 11808438e24SVarun Wadekar * registers from EL0. 11908438e24SVarun Wadekar * ---------------------------------------------------------------- 12008438e24SVarun Wadekar */ 12108438e24SVarun Wadekar mrs x0, cntkctl_el1 12208438e24SVarun Wadekar orr x0, x0, #EL0VCTEN_BIT 12308438e24SVarun Wadekar msr cntkctl_el1, x0 12408438e24SVarun Wadekar.endm 12508438e24SVarun Wadekar 12608438e24SVarun Wadekar /* ----------------------------------------------------- 12771cb26eaSVarun Wadekar * unsigned int plat_is_my_cpu_primary(void); 12808438e24SVarun Wadekar * 12908438e24SVarun Wadekar * This function checks if this is the Primary CPU 13008438e24SVarun Wadekar * ----------------------------------------------------- 13108438e24SVarun Wadekar */ 13271cb26eaSVarun Wadekarfunc plat_is_my_cpu_primary 13371cb26eaSVarun Wadekar mrs x0, mpidr_el1 13408438e24SVarun Wadekar and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 13508438e24SVarun Wadekar cmp x0, #TEGRA_PRIMARY_CPU 13608438e24SVarun Wadekar cset x0, eq 13708438e24SVarun Wadekar ret 13871cb26eaSVarun Wadekarendfunc plat_is_my_cpu_primary 13908438e24SVarun Wadekar 140b627d083SVarun Wadekar /* ---------------------------------------------------------- 14171cb26eaSVarun Wadekar * unsigned int plat_my_core_pos(void); 14208438e24SVarun Wadekar * 143b627d083SVarun Wadekar * result: CorePos = CoreId + (ClusterId * cpus per cluster) 1443bab03ebSKalyani Chidambaram * Registers clobbered: x0, x8 145b627d083SVarun Wadekar * ---------------------------------------------------------- 14608438e24SVarun Wadekar */ 14771cb26eaSVarun Wadekarfunc plat_my_core_pos 1483bab03ebSKalyani Chidambaram mov x8, x30 14971cb26eaSVarun Wadekar mrs x0, mpidr_el1 1503bab03ebSKalyani Chidambaram bl plat_core_pos_by_mpidr 1513bab03ebSKalyani Chidambaram ret x8 15271cb26eaSVarun Wadekarendfunc plat_my_core_pos 15371cb26eaSVarun Wadekar 15471cb26eaSVarun Wadekar /* ----------------------------------------------------- 15571cb26eaSVarun Wadekar * unsigned long plat_get_my_entrypoint (void); 15671cb26eaSVarun Wadekar * 15771cb26eaSVarun Wadekar * Main job of this routine is to distinguish between 15871cb26eaSVarun Wadekar * a cold and warm boot. If the tegra_sec_entry_point for 15971cb26eaSVarun Wadekar * this CPU is present, then it's a warm boot. 16071cb26eaSVarun Wadekar * 16171cb26eaSVarun Wadekar * ----------------------------------------------------- 16271cb26eaSVarun Wadekar */ 16371cb26eaSVarun Wadekarfunc plat_get_my_entrypoint 16471cb26eaSVarun Wadekar adr x1, tegra_sec_entry_point 16571cb26eaSVarun Wadekar ldr x0, [x1] 16671cb26eaSVarun Wadekar ret 16771cb26eaSVarun Wadekarendfunc plat_get_my_entrypoint 16808438e24SVarun Wadekar 16908438e24SVarun Wadekar /* ----------------------------------------------------- 170bde81dccSVarun Wadekar * int platform_get_core_pos(int mpidr); 171bde81dccSVarun Wadekar * 172b627d083SVarun Wadekar * result: CorePos = (ClusterId * cpus per cluster) + 173bde81dccSVarun Wadekar * CoreId 174bde81dccSVarun Wadekar * ----------------------------------------------------- 175bde81dccSVarun Wadekar */ 176bde81dccSVarun Wadekarfunc platform_get_core_pos 177bde81dccSVarun Wadekar and x1, x0, #MPIDR_CPU_MASK 178bde81dccSVarun Wadekar and x0, x0, #MPIDR_CLUSTER_MASK 179b627d083SVarun Wadekar lsr x0, x0, #MPIDR_AFFINITY_BITS 180b627d083SVarun Wadekar mov x2, #PLATFORM_MAX_CPUS_PER_CLUSTER 181b627d083SVarun Wadekar mul x0, x0, x2 182b627d083SVarun Wadekar add x0, x1, x0 183bde81dccSVarun Wadekar ret 184bde81dccSVarun Wadekarendfunc platform_get_core_pos 185bde81dccSVarun Wadekar 186bde81dccSVarun Wadekar /* ----------------------------------------------------- 18708438e24SVarun Wadekar * void plat_secondary_cold_boot_setup (void); 18808438e24SVarun Wadekar * 18908438e24SVarun Wadekar * This function performs any platform specific actions 19008438e24SVarun Wadekar * needed for a secondary cpu after a cold reset. Right 19108438e24SVarun Wadekar * now this is a stub function. 19208438e24SVarun Wadekar * ----------------------------------------------------- 19308438e24SVarun Wadekar */ 19408438e24SVarun Wadekarfunc plat_secondary_cold_boot_setup 19508438e24SVarun Wadekar mov x0, #0 19608438e24SVarun Wadekar ret 19708438e24SVarun Wadekarendfunc plat_secondary_cold_boot_setup 19808438e24SVarun Wadekar 19908438e24SVarun Wadekar /* -------------------------------------------------------- 20008438e24SVarun Wadekar * void platform_mem_init (void); 20108438e24SVarun Wadekar * 20208438e24SVarun Wadekar * Any memory init, relocation to be done before the 20308438e24SVarun Wadekar * platform boots. Called very early in the boot process. 20408438e24SVarun Wadekar * -------------------------------------------------------- 20508438e24SVarun Wadekar */ 20608438e24SVarun Wadekarfunc platform_mem_init 20708438e24SVarun Wadekar mov x0, #0 20808438e24SVarun Wadekar ret 20908438e24SVarun Wadekarendfunc platform_mem_init 21008438e24SVarun Wadekar 21108438e24SVarun Wadekar /* --------------------------------------------------- 21208438e24SVarun Wadekar * Function to handle a platform reset and store 21308438e24SVarun Wadekar * input parameters passed by BL2. 21408438e24SVarun Wadekar * --------------------------------------------------- 21508438e24SVarun Wadekar */ 21608438e24SVarun Wadekarfunc plat_reset_handler 21708438e24SVarun Wadekar 218939dcf25SVarun Wadekar /* ---------------------------------------------------- 219939dcf25SVarun Wadekar * Verify if we are running from BL31_BASE address 220939dcf25SVarun Wadekar * ---------------------------------------------------- 221939dcf25SVarun Wadekar */ 222939dcf25SVarun Wadekar adr x18, bl31_entrypoint 223939dcf25SVarun Wadekar mov x17, #BL31_BASE 224939dcf25SVarun Wadekar cmp x18, x17 225939dcf25SVarun Wadekar b.eq 1f 226939dcf25SVarun Wadekar 227939dcf25SVarun Wadekar /* ---------------------------------------------------- 228939dcf25SVarun Wadekar * Copy the entire BL31 code to BL31_BASE if we are not 229939dcf25SVarun Wadekar * running from it already 230939dcf25SVarun Wadekar * ---------------------------------------------------- 231939dcf25SVarun Wadekar */ 232939dcf25SVarun Wadekar mov x0, x17 233939dcf25SVarun Wadekar mov x1, x18 234939dcf25SVarun Wadekar mov x2, #BL31_SIZE 235939dcf25SVarun Wadekar_loop16: 236939dcf25SVarun Wadekar cmp x2, #16 237768baf6eSDouglas Raillard b.lo _loop1 238939dcf25SVarun Wadekar ldp x3, x4, [x1], #16 239939dcf25SVarun Wadekar stp x3, x4, [x0], #16 240939dcf25SVarun Wadekar sub x2, x2, #16 241939dcf25SVarun Wadekar b _loop16 242939dcf25SVarun Wadekar /* copy byte per byte */ 243939dcf25SVarun Wadekar_loop1: 244939dcf25SVarun Wadekar cbz x2, _end 245939dcf25SVarun Wadekar ldrb w3, [x1], #1 246939dcf25SVarun Wadekar strb w3, [x0], #1 247939dcf25SVarun Wadekar subs x2, x2, #1 248939dcf25SVarun Wadekar b.ne _loop1 249939dcf25SVarun Wadekar 250939dcf25SVarun Wadekar /* ---------------------------------------------------- 251939dcf25SVarun Wadekar * Jump to BL31_BASE and start execution again 252939dcf25SVarun Wadekar * ---------------------------------------------------- 253939dcf25SVarun Wadekar */ 254939dcf25SVarun Wadekar_end: mov x0, x20 255939dcf25SVarun Wadekar mov x1, x21 256939dcf25SVarun Wadekar br x17 257939dcf25SVarun Wadekar1: 258939dcf25SVarun Wadekar 25908438e24SVarun Wadekar /* ----------------------------------- 26008438e24SVarun Wadekar * derive and save the phys_base addr 26108438e24SVarun Wadekar * ----------------------------------- 26208438e24SVarun Wadekar */ 26308438e24SVarun Wadekar adr x17, tegra_bl31_phys_base 26408438e24SVarun Wadekar ldr x18, [x17] 26508438e24SVarun Wadekar cbnz x18, 1f 26608438e24SVarun Wadekar adr x18, bl31_entrypoint 26708438e24SVarun Wadekar str x18, [x17] 26808438e24SVarun Wadekar 26908438e24SVarun Wadekar1: cpu_init_common 27008438e24SVarun Wadekar 27108438e24SVarun Wadekar ret 27208438e24SVarun Wadekarendfunc plat_reset_handler 27308438e24SVarun Wadekar 274*0ac1bf72SVarun Wadekar /* ------------------------------------------------------ 275*0ac1bf72SVarun Wadekar * int32_t plat_core_pos_by_mpidr(u_register_t mpidr) 276*0ac1bf72SVarun Wadekar * 277*0ac1bf72SVarun Wadekar * This function implements a part of the critical 278*0ac1bf72SVarun Wadekar * interface between the psci generic layer and the 279*0ac1bf72SVarun Wadekar * platform that allows the former to query the platform 280*0ac1bf72SVarun Wadekar * to convert an MPIDR to a unique linear index. An error 281*0ac1bf72SVarun Wadekar * code (-1) is returned in case the MPIDR is invalid. 282*0ac1bf72SVarun Wadekar * 283*0ac1bf72SVarun Wadekar * Clobbers: x0-x3 284*0ac1bf72SVarun Wadekar * ------------------------------------------------------ 285*0ac1bf72SVarun Wadekar */ 286*0ac1bf72SVarun Wadekarfunc plat_core_pos_by_mpidr 287*0ac1bf72SVarun Wadekar lsr x1, x0, #MPIDR_AFF0_SHIFT 288*0ac1bf72SVarun Wadekar and x1, x1, #MPIDR_AFFLVL_MASK /* core id */ 289*0ac1bf72SVarun Wadekar lsr x2, x0, #MPIDR_AFF1_SHIFT 290*0ac1bf72SVarun Wadekar and x2, x2, #MPIDR_AFFLVL_MASK /* cluster id */ 291*0ac1bf72SVarun Wadekar 292*0ac1bf72SVarun Wadekar /* core_id >= PLATFORM_MAX_CPUS_PER_CLUSTER */ 293*0ac1bf72SVarun Wadekar mov x0, #-1 294*0ac1bf72SVarun Wadekar cmp x1, #(PLATFORM_MAX_CPUS_PER_CLUSTER - 1) 295*0ac1bf72SVarun Wadekar b.gt 1f 296*0ac1bf72SVarun Wadekar 297*0ac1bf72SVarun Wadekar /* cluster_id >= PLATFORM_CLUSTER_COUNT */ 298*0ac1bf72SVarun Wadekar cmp x2, #(PLATFORM_CLUSTER_COUNT - 1) 299*0ac1bf72SVarun Wadekar b.gt 1f 300*0ac1bf72SVarun Wadekar 301*0ac1bf72SVarun Wadekar /* CorePos = CoreId + (ClusterId * cpus per cluster) */ 302*0ac1bf72SVarun Wadekar mov x3, #PLATFORM_MAX_CPUS_PER_CLUSTER 303*0ac1bf72SVarun Wadekar mul x3, x3, x2 304*0ac1bf72SVarun Wadekar add x0, x1, x3 305*0ac1bf72SVarun Wadekar 306*0ac1bf72SVarun Wadekar1: 307*0ac1bf72SVarun Wadekar ret 308*0ac1bf72SVarun Wadekarendfunc plat_core_pos_by_mpidr 309*0ac1bf72SVarun Wadekar 31008438e24SVarun Wadekar /* ---------------------------------------- 31108438e24SVarun Wadekar * Secure entrypoint function for CPU boot 31208438e24SVarun Wadekar * ---------------------------------------- 31308438e24SVarun Wadekar */ 31464726e6dSJulius Wernerfunc tegra_secure_entrypoint _align=6 31508438e24SVarun Wadekar 31608438e24SVarun Wadekar#if ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT 31708438e24SVarun Wadekar 318c195fec6SHarvey Hsieh /* -------------------------------------------------------- 319c195fec6SHarvey Hsieh * Skip the invalidate BTB workaround for Tegra210B01 SKUs. 320c195fec6SHarvey Hsieh * -------------------------------------------------------- 321c195fec6SHarvey Hsieh */ 322c195fec6SHarvey Hsieh mov x0, #TEGRA_MISC_BASE 323c195fec6SHarvey Hsieh add x0, x0, #HARDWARE_REVISION_OFFSET 324c195fec6SHarvey Hsieh ldr w1, [x0] 325c195fec6SHarvey Hsieh lsr w1, w1, #CHIP_ID_SHIFT 326c195fec6SHarvey Hsieh and w1, w1, #CHIP_ID_MASK 327c195fec6SHarvey Hsieh cmp w1, #TEGRA_CHIPID_TEGRA21 /* T210? */ 328c195fec6SHarvey Hsieh b.ne 2f 329c195fec6SHarvey Hsieh ldr w1, [x0] 330c195fec6SHarvey Hsieh lsr w1, w1, #MAJOR_VERSION_SHIFT 331c195fec6SHarvey Hsieh and w1, w1, #MAJOR_VERSION_MASK 332c195fec6SHarvey Hsieh cmp w1, #0x02 /* T210 B01? */ 333c195fec6SHarvey Hsieh b.eq 2f 334c195fec6SHarvey Hsieh 33508438e24SVarun Wadekar /* ------------------------------------------------------- 33608438e24SVarun Wadekar * Invalidate BTB along with I$ to remove any stale 33708438e24SVarun Wadekar * entries from the branch predictor array. 33808438e24SVarun Wadekar * ------------------------------------------------------- 33908438e24SVarun Wadekar */ 340d0e1094eSEleanor Bonnici mrs x0, CORTEX_A57_CPUACTLR_EL1 34108438e24SVarun Wadekar orr x0, x0, #1 342d0e1094eSEleanor Bonnici msr CORTEX_A57_CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */ 34308438e24SVarun Wadekar dsb sy 34408438e24SVarun Wadekar isb 34508438e24SVarun Wadekar ic iallu /* actual invalidate */ 34608438e24SVarun Wadekar dsb sy 34708438e24SVarun Wadekar isb 34808438e24SVarun Wadekar 349d0e1094eSEleanor Bonnici mrs x0, CORTEX_A57_CPUACTLR_EL1 35008438e24SVarun Wadekar bic x0, x0, #1 351d0e1094eSEleanor Bonnici msr CORTEX_A57_CPUACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */ 35208438e24SVarun Wadekar dsb sy 35308438e24SVarun Wadekar isb 35408438e24SVarun Wadekar 35508438e24SVarun Wadekar .rept 7 35608438e24SVarun Wadekar nop /* wait */ 35708438e24SVarun Wadekar .endr 35808438e24SVarun Wadekar 35908438e24SVarun Wadekar /* ----------------------------------------------- 36008438e24SVarun Wadekar * Extract OSLK bit and check if it is '1'. This 36108438e24SVarun Wadekar * bit remains '0' for A53 on warm-resets. If '1', 36208438e24SVarun Wadekar * turn off regional clock gating and request warm 36308438e24SVarun Wadekar * reset. 36408438e24SVarun Wadekar * ----------------------------------------------- 36508438e24SVarun Wadekar */ 36608438e24SVarun Wadekar mrs x0, oslsr_el1 36708438e24SVarun Wadekar and x0, x0, #2 36808438e24SVarun Wadekar mrs x1, mpidr_el1 36908438e24SVarun Wadekar bics xzr, x0, x1, lsr #7 /* 0 = slow cluster or warm reset */ 37008438e24SVarun Wadekar b.eq restore_oslock 37108438e24SVarun Wadekar mov x0, xzr 37208438e24SVarun Wadekar msr oslar_el1, x0 /* os lock stays 0 across warm reset */ 37308438e24SVarun Wadekar mov x3, #3 37408438e24SVarun Wadekar movz x4, #0x8000, lsl #48 375d0e1094eSEleanor Bonnici msr CORTEX_A57_CPUACTLR_EL1, x4 /* turn off RCG */ 37608438e24SVarun Wadekar isb 37708438e24SVarun Wadekar msr rmr_el3, x3 /* request warm reset */ 37808438e24SVarun Wadekar isb 37908438e24SVarun Wadekar dsb sy 38008438e24SVarun Wadekar1: wfi 38108438e24SVarun Wadekar b 1b 38208438e24SVarun Wadekar 38308438e24SVarun Wadekar /* -------------------------------------------------- 38408438e24SVarun Wadekar * These nops are here so that speculative execution 38508438e24SVarun Wadekar * won't harm us before we are done with warm reset. 38608438e24SVarun Wadekar * -------------------------------------------------- 38708438e24SVarun Wadekar */ 38808438e24SVarun Wadekar .rept 65 38908438e24SVarun Wadekar nop 39008438e24SVarun Wadekar .endr 391c195fec6SHarvey Hsieh2: 39208438e24SVarun Wadekar /* -------------------------------------------------- 39308438e24SVarun Wadekar * Do not insert instructions here 39408438e24SVarun Wadekar * -------------------------------------------------- 39508438e24SVarun Wadekar */ 39608438e24SVarun Wadekar#endif 39708438e24SVarun Wadekar 39808438e24SVarun Wadekar /* -------------------------------------------------- 39908438e24SVarun Wadekar * Restore OS Lock bit 40008438e24SVarun Wadekar * -------------------------------------------------- 40108438e24SVarun Wadekar */ 40208438e24SVarun Wadekarrestore_oslock: 40308438e24SVarun Wadekar mov x0, #1 40408438e24SVarun Wadekar msr oslar_el1, x0 40508438e24SVarun Wadekar 40608438e24SVarun Wadekar /* -------------------------------------------------- 40708438e24SVarun Wadekar * Get secure world's entry point and jump to it 40808438e24SVarun Wadekar * -------------------------------------------------- 40908438e24SVarun Wadekar */ 41071cb26eaSVarun Wadekar bl plat_get_my_entrypoint 41108438e24SVarun Wadekar br x0 41208438e24SVarun Wadekarendfunc tegra_secure_entrypoint 41308438e24SVarun Wadekar 41408438e24SVarun Wadekar .data 41508438e24SVarun Wadekar .align 3 41608438e24SVarun Wadekar 41708438e24SVarun Wadekar /* -------------------------------------------------- 41871cb26eaSVarun Wadekar * CPU Secure entry point - resume from suspend 41908438e24SVarun Wadekar * -------------------------------------------------- 42008438e24SVarun Wadekar */ 42171cb26eaSVarun Wadekartegra_sec_entry_point: 42208438e24SVarun Wadekar .quad 0 42308438e24SVarun Wadekar 42408438e24SVarun Wadekar /* -------------------------------------------------- 42508438e24SVarun Wadekar * NS world's cold boot entry point 42608438e24SVarun Wadekar * -------------------------------------------------- 42708438e24SVarun Wadekar */ 42808438e24SVarun Wadekarns_image_entrypoint: 42908438e24SVarun Wadekar .quad 0 43008438e24SVarun Wadekar 43108438e24SVarun Wadekar /* -------------------------------------------------- 43208438e24SVarun Wadekar * BL31's physical base address 43308438e24SVarun Wadekar * -------------------------------------------------- 43408438e24SVarun Wadekar */ 43508438e24SVarun Wadekartegra_bl31_phys_base: 43608438e24SVarun Wadekar .quad 0 437e1084216SVarun Wadekar 438e1084216SVarun Wadekar /* -------------------------------------------------- 439e1084216SVarun Wadekar * UART controller base for console init 440e1084216SVarun Wadekar * -------------------------------------------------- 441e1084216SVarun Wadekar */ 442e1084216SVarun Wadekartegra_console_base: 443e1084216SVarun Wadekar .quad 0 444