1 /* 2 * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * Copyright (C) 2017-2023 Nuvoton Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 11 #include <arch.h> 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/console.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <drivers/ti/uart/uart_16550.h> 18 #include <lib/debugfs.h> 19 #include <lib/extensions/ras.h> 20 #include <lib/mmio.h> 21 #include <lib/xlat_tables/xlat_tables_compat.h> 22 #include <npcm845x_clock.h> 23 #include <npcm845x_gcr.h> 24 #include <npcm845x_lpuart.h> 25 #include <plat/arm/common/plat_arm.h> 26 #include <plat/common/platform.h> 27 #include <plat_npcm845x.h> 28 #include <platform_def.h> 29 30 /* 31 * Placeholder variables for copying the arguments that have been passed to 32 * BL31 from BL2. 33 */ 34 static entry_point_info_t bl32_image_ep_info; 35 static entry_point_info_t bl33_image_ep_info; 36 37 #if !RESET_TO_BL31 38 /* 39 * Check that BL31_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page 40 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2. 41 */ 42 /* CASSERT(BL31_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl31_base_overflows); */ 43 #endif /* !RESET_TO_BL31 */ 44 45 #define MAP_BL31_TOTAL MAP_REGION_FLAT( \ 46 BL31_START, \ 47 BL31_END - BL31_START, \ 48 MT_MEMORY | MT_RW | EL3_PAS) 49 50 #if SEPARATE_NOBITS_REGION 51 #define MAP_BL31_NOBITS MAP_REGION_FLAT( \ 52 BL31_NOBITS_BASE, \ 53 BL31_NOBITS_LIMIT - \ 54 BL31_NOBITS_BASE, \ 55 MT_MEMORY | MT_RW | EL3_PAS) 56 #endif /* SEPARATE_NOBITS_REGION */ 57 58 /****************************************************************************** 59 * Return a pointer to the 'entry_point_info' structure of the next image 60 * for the security state specified. BL33 corresponds to the non-secure 61 * image type while BL32 corresponds to the secure image type. 62 * A NULL pointer is returned if the image does not exist. 63 *****************************************************************************/ 64 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) 65 { 66 entry_point_info_t *next_image_info; 67 68 assert(sec_state_is_valid(type)); 69 next_image_info = (type == NON_SECURE) 70 ? &bl33_image_ep_info : &bl32_image_ep_info; 71 /* 72 * None of the images on the ARM development platforms can have 0x0 73 * as the entrypoint 74 */ 75 if (next_image_info->pc) { 76 return next_image_info; 77 } else { 78 return NULL; 79 } 80 } 81 82 int board_uart_init(void) 83 { 84 unsigned long UART_BASE_ADDR; 85 static console_t console; 86 87 #ifdef CONFIG_TARGET_ARBEL_PALLADIUM 88 UART_Init(UART0_DEV, UART_MUX_MODE1, 89 UART_BAUDRATE_115200); 90 UART_BASE_ADDR = npcm845x_get_base_uart(UART0_DEV); 91 #else 92 UART_BASE_ADDR = npcm845x_get_base_uart(UART0_DEV); 93 #endif /* CONFIG_TARGET_ARBEL_PALLADIUM */ 94 95 /* 96 * Register UART w/o initialization - 97 * A clock rate of zero means to skip the initialisation. 98 */ 99 console_16550_register((uintptr_t)UART_BASE_ADDR, 0, 0, &console); 100 101 return 0; 102 } 103 104 unsigned int plat_get_syscnt_freq2(void) 105 { 106 return (unsigned int)COUNTER_FREQUENCY; 107 } 108 109 /****************************************************************************** 110 * Perform any BL31 early platform setup common to ARM standard platforms. 111 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 112 * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be 113 * done before the MMU is initialized so that the memory layout can be used 114 * while creating page tables. BL2 has flushed this information to memory, 115 * so we are guaranteed to pick up good data. 116 *****************************************************************************/ 117 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 118 u_register_t arg2, u_register_t arg3) 119 { 120 #if RESET_TO_BL31 121 void *from_bl2 = (void *)arg0; 122 void *plat_params_from_bl2 = (void *)arg3; 123 124 if (from_bl2 != NULL) { 125 assert(from_bl2 == NULL); 126 } 127 128 if (plat_params_from_bl2 != NULL) { 129 assert(plat_params_from_bl2 == NULL); 130 } 131 #endif /* RESET_TO_BL31 */ 132 133 /* Initialize Delay timer */ 134 generic_delay_timer_init(); 135 136 /* Do Specific Board/Chip initializations */ 137 board_uart_init(); 138 139 #if RESET_TO_BL31 140 /* There are no parameters from BL2 if BL31 is a reset vector */ 141 assert(from_bl2 == NULL); 142 assert(plat_params_from_bl2 == NULL); 143 144 #ifdef BL32_BASE 145 /* Populate entry point information for BL32 */ 146 SET_PARAM_HEAD(&bl32_image_ep_info, 147 PARAM_EP, 148 VERSION_1, 149 0); 150 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 151 bl32_image_ep_info.pc = BL32_BASE; 152 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 153 154 #if defined(SPD_spmd) 155 /* 156 * SPM (hafnium in secure world) expects SPM Core manifest base address 157 * in x0, which in !RESET_TO_BL31 case loaded after base of non shared 158 * SRAM(after 4KB offset of SRAM). But in RESET_TO_BL31 case all non 159 * shared SRAM is allocated to BL31, so to avoid overwriting of manifest 160 * keep it in the last page. 161 */ 162 bl32_image_ep_info.args.arg0 = ARM_TRUSTED_SRAM_BASE + 163 PLAT_ARM_TRUSTED_SRAM_SIZE - PAGE_SIZE; 164 #endif /* SPD_spmd */ 165 #endif /* BL32_BASE */ 166 167 /* Populate entry point information for BL33 */ 168 SET_PARAM_HEAD(&bl33_image_ep_info, 169 PARAM_EP, 170 VERSION_1, 171 0); 172 173 /* 174 * Tell BL31 where the non-trusted software image 175 * is located and the entry state information 176 */ 177 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 178 /* Generic ARM code will switch to EL2, revert to EL1 */ 179 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 180 bl33_image_ep_info.spsr &= ~0x8; 181 bl33_image_ep_info.spsr |= 0x4; 182 183 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, (uint32_t)NON_SECURE); 184 185 #if defined(SPD_spmd) && !(ARM_LINUX_KERNEL_AS_BL33) 186 /* 187 * Hafnium in normal world expects its manifest address in x0, 188 * which is loaded at base of DRAM. 189 */ 190 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_DRAM1_BASE; 191 #endif /* SPD_spmd && !ARM_LINUX_KERNEL_AS_BL33 */ 192 193 #if ARM_LINUX_KERNEL_AS_BL33 194 /* 195 * According to the file ``Documentation/arm64/booting.txt`` of the 196 * Linux kernel tree, Linux expects the physical address of the device 197 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and 198 * must be 0. 199 */ 200 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; 201 bl33_image_ep_info.args.arg1 = 0U; 202 bl33_image_ep_info.args.arg2 = 0U; 203 bl33_image_ep_info.args.arg3 = 0U; 204 #endif /* ARM_LINUX_KERNEL_AS_BL33 */ 205 206 #else /* RESET_TO_BL31 */ 207 /* 208 * In debug builds, we pass a special value in 'plat_params_from_bl2' 209 * to verify platform parameters from BL2 to BL31. 210 * In release builds, it's not used. 211 */ 212 assert(((unsigned long long)plat_params_from_bl2) == 213 ARM_BL31_PLAT_PARAM_VAL); 214 215 /* 216 * Check params passed from BL2 should not be NULL, 217 */ 218 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 219 220 assert(params_from_bl2 != NULL); 221 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 222 assert(params_from_bl2->h.version >= VERSION_2); 223 224 bl_params_node_t *bl_params = params_from_bl2->head; 225 226 /* 227 * Copy BL33 and BL32 (if present), entry point information. 228 * They are stored in Secure RAM, in BL2's address space. 229 */ 230 while (bl_params != NULL) { 231 if (bl_params->image_id == BL32_IMAGE_ID) { 232 bl32_image_ep_info = *bl_params->ep_info; 233 } 234 235 if (bl_params->image_id == BL33_IMAGE_ID) { 236 bl33_image_ep_info = *bl_params->ep_info; 237 } 238 239 bl_params = bl_params->next_params_info; 240 } 241 242 if (bl33_image_ep_info.pc == 0U) { 243 panic(); 244 } 245 #endif /* RESET_TO_BL31 */ 246 } 247 248 /******************************************************************************* 249 * Perform any BL31 platform setup common to ARM standard platforms 250 ******************************************************************************/ 251 void bl31_platform_setup(void) 252 { 253 /* Initialize the GIC driver, cpu and distributor interfaces */ 254 plat_gic_driver_init(); 255 plat_gic_init(); 256 257 #if RESET_TO_BL31 258 #if defined(PLAT_ARM_MEM_PROT_ADDR) 259 arm_nor_psci_do_dyn_mem_protect(); 260 #endif /* PLAT_ARM_MEM_PROT_ADDR */ 261 #else 262 /* 263 * In this soluction, we also do the security initialzation 264 * even when BL31 is not in the reset vector 265 */ 266 npcm845x_security_setup(); 267 #endif /* RESET_TO_BL31 */ 268 269 /* Enable and initialize the System level generic timer */ 270 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 271 CNTCR_FCREQ(0U) | CNTCR_EN); 272 273 /* Initialize power controller before setting up topology */ 274 plat_arm_pwrc_setup(); 275 276 #if RAS_EXTENSION 277 ras_init(); 278 #endif 279 280 #if USE_DEBUGFS 281 debugfs_init(); 282 #endif /* USE_DEBUGFS */ 283 } 284 285 void arm_console_runtime_init(void) 286 { 287 /* Added in order to ignore the original weak function */ 288 } 289 290 void plat_arm_program_trusted_mailbox(uintptr_t address) 291 { 292 /* 293 * now we don't use ARM mailbox, 294 * so that function added to ignore the weak one 295 */ 296 } 297 298 void __init bl31_plat_arch_setup(void) 299 { 300 npcm845x_bl31_plat_arch_setup(); 301 } 302 303 void __init plat_arm_pwrc_setup(void) 304 { 305 /* NPCM850 is always powered so no need for power control */ 306 } 307 308 void __init npcm845x_bl31_plat_arch_setup(void) 309 { 310 const mmap_region_t bl_regions[] = { 311 MAP_BL31_TOTAL, 312 #if SEPARATE_NOBITS_REGION 313 MAP_BL31_NOBITS, 314 #endif /* SEPARATE_NOBITS_REGION */ 315 ARM_MAP_BL_RO, 316 #if USE_ROMLIB 317 ARM_MAP_ROMLIB_CODE, 318 ARM_MAP_ROMLIB_DATA, 319 #endif /* USE_ROMLIB */ 320 #if USE_COHERENT_MEM 321 ARM_MAP_BL_COHERENT_RAM, 322 #endif /* USE_COHERENT_MEM */ 323 ARM_MAP_SHARED_RAM, 324 #ifdef SECONDARY_BRINGUP 325 ARM_MAP_NS_DRAM1, 326 #ifdef BL32_BASE 327 ARM_MAP_BL32_CORE_MEM 328 #endif /* BL32_BASE */ 329 #endif /* SECONDARY_BRINGUP */ 330 {0} 331 }; 332 setup_page_tables(bl_regions, plat_arm_get_mmap()); 333 enable_mmu_el3(0U); 334 } 335