1 /* 2 * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * Copyright (C) 2017-2023 Nuvoton Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 11 #include <arch.h> 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/console.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <drivers/ti/uart/uart_16550.h> 18 #include <lib/debugfs.h> 19 #include <lib/extensions/ras.h> 20 #include <lib/mmio.h> 21 #include <lib/xlat_tables/xlat_tables_compat.h> 22 #include <npcm845x_clock.h> 23 #include <npcm845x_gcr.h> 24 #include <npcm845x_lpuart.h> 25 #include <plat/arm/common/plat_arm.h> 26 #include <plat/common/platform.h> 27 #include <plat_npcm845x.h> 28 #include <platform_def.h> 29 30 /* 31 * Placeholder variables for copying the arguments that have been passed to 32 * BL31 from BL2. 33 */ 34 static entry_point_info_t bl32_image_ep_info; 35 static entry_point_info_t bl33_image_ep_info; 36 37 #if !RESET_TO_BL31 38 /* 39 * Check that BL31_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page 40 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2. 41 */ 42 /* CASSERT(BL31_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl31_base_overflows); */ 43 #endif /* !RESET_TO_BL31 */ 44 45 #define MAP_BL31_TOTAL MAP_REGION_FLAT( \ 46 BL31_START, \ 47 BL31_END - BL31_START, \ 48 MT_MEMORY | MT_RW | EL3_PAS) 49 50 #if RECLAIM_INIT_CODE 51 IMPORT_SYM(unsigned long, __INIT_CODE_START__, BL_INIT_CODE_BASE); 52 IMPORT_SYM(unsigned long, __INIT_CODE_END__, BL_CODE_END_UNALIGNED); 53 54 #define BL_INIT_CODE_END ((BL_CODE_END_UNALIGNED + PAGE_SIZE - 1) & \ 55 ~(PAGE_SIZE - 1)) 56 57 #define MAP_BL_INIT_CODE MAP_REGION_FLAT( \ 58 BL_INIT_CODE_BASE, \ 59 BL_INIT_CODE_END - \ 60 BL_INIT_CODE_BASE, \ 61 MT_CODE | MT_SECURE) 62 #endif /* RECLAIM_INIT_CODE */ 63 64 #if SEPARATE_NOBITS_REGION 65 #define MAP_BL31_NOBITS MAP_REGION_FLAT( \ 66 BL31_NOBITS_BASE, \ 67 BL31_NOBITS_LIMIT - \ 68 BL31_NOBITS_BASE, \ 69 MT_MEMORY | MT_RW | EL3_PAS) 70 #endif /* SEPARATE_NOBITS_REGION */ 71 72 /****************************************************************************** 73 * Return a pointer to the 'entry_point_info' structure of the next image 74 * for the security state specified. BL33 corresponds to the non-secure 75 * image type while BL32 corresponds to the secure image type. 76 * A NULL pointer is returned if the image does not exist. 77 *****************************************************************************/ 78 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) 79 { 80 entry_point_info_t *next_image_info; 81 82 assert(sec_state_is_valid(type)); 83 next_image_info = (type == NON_SECURE) 84 ? &bl33_image_ep_info : &bl32_image_ep_info; 85 /* 86 * None of the images on the ARM development platforms can have 0x0 87 * as the entrypoint 88 */ 89 if (next_image_info->pc) { 90 return next_image_info; 91 } else { 92 return NULL; 93 } 94 } 95 96 int board_uart_init(void) 97 { 98 unsigned long UART_BASE_ADDR; 99 static console_t console; 100 101 #ifdef CONFIG_TARGET_ARBEL_PALLADIUM 102 UART_Init(UART0_DEV, UART_MUX_MODE1, 103 UART_BAUDRATE_115200); 104 UART_BASE_ADDR = npcm845x_get_base_uart(UART0_DEV); 105 #else 106 UART_BASE_ADDR = npcm845x_get_base_uart(UART0_DEV); 107 #endif /* CONFIG_TARGET_ARBEL_PALLADIUM */ 108 109 /* 110 * Register UART w/o initialization - 111 * A clock rate of zero means to skip the initialisation. 112 */ 113 console_16550_register((uintptr_t)UART_BASE_ADDR, 0, 0, &console); 114 115 return 0; 116 } 117 118 unsigned int plat_get_syscnt_freq2(void) 119 { 120 /* 121 * Do not overwrite the value set by BootBlock 122 */ 123 return (unsigned int)read_cntfrq_el0(); 124 } 125 126 /****************************************************************************** 127 * Perform any BL31 early platform setup common to ARM standard platforms. 128 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 129 * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be 130 * done before the MMU is initialized so that the memory layout can be used 131 * while creating page tables. BL2 has flushed this information to memory, 132 * so we are guaranteed to pick up good data. 133 *****************************************************************************/ 134 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 135 u_register_t arg2, u_register_t arg3) 136 { 137 arg0 = arg1 = arg2 = arg3 = 0; 138 #if RESET_TO_BL31 139 void *from_bl2 = (void *)arg0; 140 void *plat_params_from_bl2 = (void *)arg3; 141 142 if (from_bl2 != NULL) { 143 assert(from_bl2 == NULL); 144 } 145 146 if (plat_params_from_bl2 != NULL) { 147 assert(plat_params_from_bl2 == NULL); 148 } 149 #endif /* RESET_TO_BL31 */ 150 151 /* Initialize Delay timer */ 152 generic_delay_timer_init(); 153 154 /* Do Specific Board/Chip initializations */ 155 board_uart_init(); 156 157 #if RESET_TO_BL31 158 /* There are no parameters from BL2 if BL31 is a reset vector */ 159 assert(from_bl2 == NULL); 160 assert(plat_params_from_bl2 == NULL); 161 162 #ifdef BL32_BASE 163 /* Populate entry point information for BL32 */ 164 SET_PARAM_HEAD(&bl32_image_ep_info, 165 PARAM_EP, 166 VERSION_1, 167 0); 168 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 169 bl32_image_ep_info.pc = BL32_BASE; 170 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 171 172 #if defined(SPD_spmd) 173 /* 174 * SPM (hafnium in secure world) expects SPM Core manifest base address 175 * in x0, which in !RESET_TO_BL31 case loaded after base of non shared 176 * SRAM(after 4KB offset of SRAM). But in RESET_TO_BL31 case all non 177 * shared SRAM is allocated to BL31, so to avoid overwriting of manifest 178 * keep it in the last page. 179 */ 180 bl32_image_ep_info.args.arg0 = ARM_TRUSTED_SRAM_BASE + 181 PLAT_ARM_TRUSTED_SRAM_SIZE - PAGE_SIZE; 182 #endif /* SPD_spmd */ 183 #endif /* BL32_BASE */ 184 185 /* Populate entry point information for BL33 */ 186 SET_PARAM_HEAD(&bl33_image_ep_info, 187 PARAM_EP, 188 VERSION_1, 189 0); 190 191 /* 192 * Tell BL31 where the non-trusted software image 193 * is located and the entry state information 194 */ 195 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 196 /* Generic ARM code will switch to EL2, revert to EL1 */ 197 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 198 bl33_image_ep_info.spsr &= ~0x8; 199 bl33_image_ep_info.spsr |= 0x4; 200 201 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, (uint32_t)NON_SECURE); 202 203 #if defined(SPD_spmd) && !(ARM_LINUX_KERNEL_AS_BL33) 204 /* 205 * Hafnium in normal world expects its manifest address in x0, 206 * which is loaded at base of DRAM. 207 */ 208 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_DRAM1_BASE; 209 #endif /* SPD_spmd && !ARM_LINUX_KERNEL_AS_BL33 */ 210 211 #if ARM_LINUX_KERNEL_AS_BL33 212 /* 213 * According to the file ``Documentation/arm64/booting.txt`` of the 214 * Linux kernel tree, Linux expects the physical address of the device 215 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and 216 * must be 0. 217 */ 218 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; 219 bl33_image_ep_info.args.arg1 = 0U; 220 bl33_image_ep_info.args.arg2 = 0U; 221 bl33_image_ep_info.args.arg3 = 0U; 222 #endif /* ARM_LINUX_KERNEL_AS_BL33 */ 223 224 #else /* RESET_TO_BL31 */ 225 /* 226 * In debug builds, we pass a special value in 'plat_params_from_bl2' 227 * to verify platform parameters from BL2 to BL31. 228 * In release builds, it's not used. 229 */ 230 assert(((unsigned long long)plat_params_from_bl2) == 231 ARM_BL31_PLAT_PARAM_VAL); 232 233 /* 234 * Check params passed from BL2 should not be NULL, 235 */ 236 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 237 238 assert(params_from_bl2 != NULL); 239 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 240 assert(params_from_bl2->h.version >= VERSION_2); 241 242 bl_params_node_t *bl_params = params_from_bl2->head; 243 244 /* 245 * Copy BL33 and BL32 (if present), entry point information. 246 * They are stored in Secure RAM, in BL2's address space. 247 */ 248 while (bl_params != NULL) { 249 if (bl_params->image_id == BL32_IMAGE_ID) { 250 bl32_image_ep_info = *bl_params->ep_info; 251 } 252 253 if (bl_params->image_id == BL33_IMAGE_ID) { 254 bl33_image_ep_info = *bl_params->ep_info; 255 } 256 257 bl_params = bl_params->next_params_info; 258 } 259 260 if (bl33_image_ep_info.pc == 0U) { 261 panic(); 262 } 263 #endif /* RESET_TO_BL31 */ 264 } 265 266 /******************************************************************************* 267 * Perform any BL31 platform setup common to ARM standard platforms 268 ******************************************************************************/ 269 void bl31_platform_setup(void) 270 { 271 /* Initialize the GIC driver, cpu and distributor interfaces */ 272 plat_gic_driver_init(); 273 plat_gic_init(); 274 275 #if RESET_TO_BL31 276 #if defined(PLAT_ARM_MEM_PROT_ADDR) 277 arm_nor_psci_do_dyn_mem_protect(); 278 #endif /* PLAT_ARM_MEM_PROT_ADDR */ 279 #else 280 /* 281 * In this soluction, we also do the security initialzation 282 * even when BL31 is not in the reset vector 283 */ 284 npcm845x_security_setup(); 285 #endif /* RESET_TO_BL31 */ 286 287 /* Enable and initialize the System level generic timer */ 288 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 289 CNTCR_FCREQ(0U) | CNTCR_EN); 290 291 /* Initialize power controller before setting up topology */ 292 plat_arm_pwrc_setup(); 293 294 #if RAS_EXTENSION 295 ras_init(); 296 #endif 297 298 #if USE_DEBUGFS 299 debugfs_init(); 300 #endif /* USE_DEBUGFS */ 301 } 302 303 void arm_console_runtime_init(void) 304 { 305 /* Added in order to ignore the original weak function */ 306 } 307 308 void plat_arm_program_trusted_mailbox(uintptr_t address) 309 { 310 /* 311 * now we don't use ARM mailbox, 312 * so that function added to ignore the weak one 313 */ 314 } 315 316 void __init bl31_plat_arch_setup(void) 317 { 318 npcm845x_bl31_plat_arch_setup(); 319 } 320 321 void __init plat_arm_pwrc_setup(void) 322 { 323 /* NPCM850 is always powered so no need for power control */ 324 } 325 326 void __init npcm845x_bl31_plat_arch_setup(void) 327 { 328 const mmap_region_t bl_regions[] = { 329 MAP_BL31_TOTAL, 330 ARM_MAP_BL_RO, 331 #if USE_COHERENT_MEM 332 ARM_MAP_BL_COHERENT_RAM, 333 #endif /* USE_COHERENT_MEM */ 334 ARM_MAP_SHARED_RAM, 335 {0} 336 }; 337 setup_page_tables(bl_regions, plat_arm_get_mmap()); 338 enable_mmu_el3(0U); 339 } 340