xref: /rk3399_ARM-atf/plat/mediatek/mt8196/plat_config.mk (revision d4e6f98d7f8b33ebd7706e8a440c568262500e21)
1a65fadfbSGavin Liu#
2*d4e6f98dSHope Wang# Copyright (c) 2025, MediaTek Inc. All rights reserved.
3a65fadfbSGavin Liu#
4a65fadfbSGavin Liu# SPDX-License-Identifier: BSD-3-Clause
5a65fadfbSGavin Liu#
6a65fadfbSGavin Liu
7a65fadfbSGavin Liu# Separate text code and read only data
8a65fadfbSGavin LiuSEPARATE_CODE_AND_RODATA := 1
9a65fadfbSGavin Liu
10a65fadfbSGavin Liu# ARMv8.2 and above need enable HW assist coherence
11a65fadfbSGavin LiuHW_ASSISTED_COHERENCY := 1
12a65fadfbSGavin Liu
13a65fadfbSGavin Liu# No need coherency memory because of HW assistency
14a65fadfbSGavin LiuUSE_COHERENT_MEM := 0
15a65fadfbSGavin Liu
16a65fadfbSGavin Liu# GIC600
17a65fadfbSGavin LiuGICV3_SUPPORT_GIC600 := 1
18a65fadfbSGavin Liu
19a65fadfbSGavin Liu#
20a65fadfbSGavin Liu# MTK options
21a65fadfbSGavin Liu#
22a65fadfbSGavin LiuPLAT_EXTRA_RODATA_INCLUDES := 1
23a65fadfbSGavin LiuUSE_PMIC_WRAP_INIT_V2 := 1
24a65fadfbSGavin Liu
25a65fadfbSGavin Liu# Configs for A78 and A55
26a65fadfbSGavin LiuCTX_INCLUDE_AARCH32_REGS := 0
27a65fadfbSGavin Liu
28a65fadfbSGavin LiuCONFIG_ARCH_ARM_V9 := y
295e5c57d5SKarl LiCONFIG_MTK_APUSYS_CE_SUPPORT := y
309059a375SKarl LiCONFIG_MTK_APUSYS_EMI_SUPPORT := n
315e5c57d5SKarl LiCONFIG_MTK_APUSYS_LOGTOP_SUPPORT := y
32e534d4f6SKarl LiCONFIG_MTK_APUSYS_RV_APUMMU_SUPPORT := y
335e5c57d5SKarl LiCONFIG_MTK_APUSYS_RV_COREDUMP_WA_SUPPORT := y
342d134d28SKarl LiCONFIG_MTK_APUSYS_RV_IOMMU_HW_SEM_SUPPORT := y
35e534d4f6SKarl LiCONFIG_MTK_APUSYS_SEC_CTRL := y
365e5c57d5SKarl LiCONFIG_MTK_APUSYS_SETUP_CE := y
37a65fadfbSGavin LiuCONFIG_MTK_MCUSYS := y
38a65fadfbSGavin LiuMCUSYS_VERSION := v1
39a65fadfbSGavin LiuCONFIG_MTK_PM_SUPPORT := y
40a65fadfbSGavin LiuCONFIG_MTK_PM_ARCH := 9_0
41a65fadfbSGavin LiuCONFIG_MTK_CPU_PM_SUPPORT := y
42a65fadfbSGavin LiuCONFIG_MTK_CPU_PM_ARCH := 5_4
43a65fadfbSGavin LiuCONFIG_MTK_SMP_EN := n
44a65fadfbSGavin LiuCONFIG_MTK_CPU_SUSPEND_EN := y
45a65fadfbSGavin LiuCONFIG_MTK_SPM_VERSION := mt8196
46a65fadfbSGavin LiuCONFIG_MTK_SUPPORT_SYSTEM_SUSPEND := y
47a1763ae9SXiangzhi TangCONFIG_MTK_TINYSYS_VCP := y
48a65fadfbSGavin LiuCPU_PM_TINYSYS_SUPPORT := y
49a65fadfbSGavin LiuMTK_PUBEVENT_ENABLE := y
50*d4e6f98dSHope WangCONFIG_MTK_PMIC := y
51*d4e6f98dSHope WangCONFIG_MTK_PMIC_LOWPOWER := y
52*d4e6f98dSHope WangCONFIG_MTK_PMIC_SHUTDOWN_CFG := y
53*d4e6f98dSHope WangCONFIG_MTK_PMIC_SPT_SUPPORT := n
54*d4e6f98dSHope Wang
55*d4e6f98dSHope WangPMIC_CHIP := mt6363
56a65fadfbSGavin Liu
57a65fadfbSGavin LiuENABLE_FEAT_AMU := 1
58a65fadfbSGavin LiuENABLE_FEAT_ECV := 1
59a65fadfbSGavin LiuENABLE_FEAT_FGT := 1
60a65fadfbSGavin LiuENABLE_FEAT_HCX := 1
61a65fadfbSGavin LiuENABLE_SVE_FOR_SWD := 1
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