1*a65fadfbSGavin Liu /* 2*a65fadfbSGavin Liu * Copyright (c) 2024, Mediatek Inc. All rights reserved. 3*a65fadfbSGavin Liu * 4*a65fadfbSGavin Liu * SPDX-License-Identifier: BSD-3-Clause 5*a65fadfbSGavin Liu */ 6*a65fadfbSGavin Liu 7*a65fadfbSGavin Liu #ifndef PLATFORM_DEF_H 8*a65fadfbSGavin Liu #define PLATFORM_DEF_H 9*a65fadfbSGavin Liu 10*a65fadfbSGavin Liu #include <arch.h> 11*a65fadfbSGavin Liu #include <plat/common/common_def.h> 12*a65fadfbSGavin Liu 13*a65fadfbSGavin Liu #include <arch_def.h> 14*a65fadfbSGavin Liu 15*a65fadfbSGavin Liu #define PLAT_PRIMARY_CPU (0x0) 16*a65fadfbSGavin Liu 17*a65fadfbSGavin Liu #define MT_GIC_BASE (0x0C400000) 18*a65fadfbSGavin Liu #define MCUCFG_BASE (0x0C000000) 19*a65fadfbSGavin Liu #define MCUCFG_REG_SIZE (0x50000) 20*a65fadfbSGavin Liu #define IO_PHYS (0x10000000) 21*a65fadfbSGavin Liu 22*a65fadfbSGavin Liu /* Aggregate of all devices for MMU mapping */ 23*a65fadfbSGavin Liu #define MTK_DEV_RNG1_BASE (IO_PHYS) 24*a65fadfbSGavin Liu #define MTK_DEV_RNG1_SIZE (0x10000000) 25*a65fadfbSGavin Liu 26*a65fadfbSGavin Liu #define TOPCKGEN_BASE (IO_PHYS) 27*a65fadfbSGavin Liu 28*a65fadfbSGavin Liu /******************************************************************************* 29*a65fadfbSGavin Liu * AUDIO related constants 30*a65fadfbSGavin Liu ******************************************************************************/ 31*a65fadfbSGavin Liu #define AUDIO_BASE (IO_PHYS + 0x0a110000) 32*a65fadfbSGavin Liu 33*a65fadfbSGavin Liu /******************************************************************************* 34*a65fadfbSGavin Liu * SPM related constants 35*a65fadfbSGavin Liu ******************************************************************************/ 36*a65fadfbSGavin Liu #define SPM_BASE (IO_PHYS + 0x0C004000) 37*a65fadfbSGavin Liu 38*a65fadfbSGavin Liu /******************************************************************************* 39*a65fadfbSGavin Liu * UART related constants 40*a65fadfbSGavin Liu ******************************************************************************/ 41*a65fadfbSGavin Liu #define UART0_BASE (IO_PHYS + 0x06000000) 42*a65fadfbSGavin Liu #define UART_BAUDRATE (115200) 43*a65fadfbSGavin Liu 44*a65fadfbSGavin Liu /******************************************************************************* 45*a65fadfbSGavin Liu * Infra IOMMU related constants 46*a65fadfbSGavin Liu ******************************************************************************/ 47*a65fadfbSGavin Liu #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) 48*a65fadfbSGavin Liu #define INFRACFG_AO_MEM_BASE (IO_PHYS + 0x00404000) 49*a65fadfbSGavin Liu #define PERICFG_AO_BASE (IO_PHYS + 0x06630000) 50*a65fadfbSGavin Liu #define PERICFG_AO_REG_SIZE (0x1000) 51*a65fadfbSGavin Liu 52*a65fadfbSGavin Liu /******************************************************************************* 53*a65fadfbSGavin Liu * GIC-600 & interrupt handling related constants 54*a65fadfbSGavin Liu ******************************************************************************/ 55*a65fadfbSGavin Liu /* Base MTK_platform compatible GIC memory map */ 56*a65fadfbSGavin Liu #define BASE_GICD_BASE (MT_GIC_BASE) 57*a65fadfbSGavin Liu #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 58*a65fadfbSGavin Liu #define MTK_GIC_REG_SIZE 0x400000 59*a65fadfbSGavin Liu 60*a65fadfbSGavin Liu /******************************************************************************* 61*a65fadfbSGavin Liu * MM IOMMU & SMI related constants 62*a65fadfbSGavin Liu ******************************************************************************/ 63*a65fadfbSGavin Liu #define SMI_LARB_0_BASE (IO_PHYS + 0x0c022000) 64*a65fadfbSGavin Liu #define SMI_LARB_1_BASE (IO_PHYS + 0x0c023000) 65*a65fadfbSGavin Liu #define SMI_LARB_2_BASE (IO_PHYS + 0x0c102000) 66*a65fadfbSGavin Liu #define SMI_LARB_3_BASE (IO_PHYS + 0x0c103000) 67*a65fadfbSGavin Liu #define SMI_LARB_4_BASE (IO_PHYS + 0x04013000) 68*a65fadfbSGavin Liu #define SMI_LARB_5_BASE (IO_PHYS + 0x04f02000) 69*a65fadfbSGavin Liu #define SMI_LARB_6_BASE (IO_PHYS + 0x04f03000) 70*a65fadfbSGavin Liu #define SMI_LARB_7_BASE (IO_PHYS + 0x04e04000) 71*a65fadfbSGavin Liu #define SMI_LARB_9_BASE (IO_PHYS + 0x05001000) 72*a65fadfbSGavin Liu #define SMI_LARB_10_BASE (IO_PHYS + 0x05120000) 73*a65fadfbSGavin Liu #define SMI_LARB_11A_BASE (IO_PHYS + 0x05230000) 74*a65fadfbSGavin Liu #define SMI_LARB_11B_BASE (IO_PHYS + 0x05530000) 75*a65fadfbSGavin Liu #define SMI_LARB_11C_BASE (IO_PHYS + 0x05630000) 76*a65fadfbSGavin Liu #define SMI_LARB_12_BASE (IO_PHYS + 0x05340000) 77*a65fadfbSGavin Liu #define SMI_LARB_13_BASE (IO_PHYS + 0x06001000) 78*a65fadfbSGavin Liu #define SMI_LARB_14_BASE (IO_PHYS + 0x06002000) 79*a65fadfbSGavin Liu #define SMI_LARB_15_BASE (IO_PHYS + 0x05140000) 80*a65fadfbSGavin Liu #define SMI_LARB_16A_BASE (IO_PHYS + 0x06008000) 81*a65fadfbSGavin Liu #define SMI_LARB_16B_BASE (IO_PHYS + 0x0600a000) 82*a65fadfbSGavin Liu #define SMI_LARB_17A_BASE (IO_PHYS + 0x06009000) 83*a65fadfbSGavin Liu #define SMI_LARB_17B_BASE (IO_PHYS + 0x0600b000) 84*a65fadfbSGavin Liu #define SMI_LARB_19_BASE (IO_PHYS + 0x0a010000) 85*a65fadfbSGavin Liu #define SMI_LARB_21_BASE (IO_PHYS + 0x0802e000) 86*a65fadfbSGavin Liu #define SMI_LARB_23_BASE (IO_PHYS + 0x0800d000) 87*a65fadfbSGavin Liu #define SMI_LARB_27_BASE (IO_PHYS + 0x07201000) 88*a65fadfbSGavin Liu #define SMI_LARB_28_BASE (IO_PHYS + 0x00000000) 89*a65fadfbSGavin Liu #define SMI_LARB_REG_RNG_SIZE (0x1000) 90*a65fadfbSGavin Liu 91*a65fadfbSGavin Liu /******************************************************************************* 92*a65fadfbSGavin Liu * APMIXEDSYS related constants 93*a65fadfbSGavin Liu ******************************************************************************/ 94*a65fadfbSGavin Liu #define APMIXEDSYS (IO_PHYS + 0x0000C000) 95*a65fadfbSGavin Liu 96*a65fadfbSGavin Liu /******************************************************************************* 97*a65fadfbSGavin Liu * VPPSYS related constants 98*a65fadfbSGavin Liu ******************************************************************************/ 99*a65fadfbSGavin Liu #define VPPSYS0_BASE (IO_PHYS + 0x04000000) 100*a65fadfbSGavin Liu #define VPPSYS1_BASE (IO_PHYS + 0x04f00000) 101*a65fadfbSGavin Liu 102*a65fadfbSGavin Liu /******************************************************************************* 103*a65fadfbSGavin Liu * VDOSYS related constants 104*a65fadfbSGavin Liu ******************************************************************************/ 105*a65fadfbSGavin Liu #define VDOSYS0_BASE (IO_PHYS + 0x0C01D000) 106*a65fadfbSGavin Liu #define VDOSYS1_BASE (IO_PHYS + 0x0C100000) 107*a65fadfbSGavin Liu 108*a65fadfbSGavin Liu /******************************************************************************* 109*a65fadfbSGavin Liu * EMI MPU related constants 110*a65fadfbSGavin Liu *******************************************************************************/ 111*a65fadfbSGavin Liu #define EMI_MPU_BASE (IO_PHYS + 0x00428000) 112*a65fadfbSGavin Liu #define SUB_EMI_MPU_BASE (IO_PHYS + 0x00528000) 113*a65fadfbSGavin Liu 114*a65fadfbSGavin Liu /******************************************************************************* 115*a65fadfbSGavin Liu * System counter frequency related constants 116*a65fadfbSGavin Liu ******************************************************************************/ 117*a65fadfbSGavin Liu #define SYS_COUNTER_FREQ_IN_HZ (13000000) 118*a65fadfbSGavin Liu #define SYS_COUNTER_FREQ_IN_MHZ (13) 119*a65fadfbSGavin Liu 120*a65fadfbSGavin Liu /******************************************************************************* 121*a65fadfbSGavin Liu * Generic platform constants 122*a65fadfbSGavin Liu ******************************************************************************/ 123*a65fadfbSGavin Liu #define PLATFORM_STACK_SIZE (0x800) 124*a65fadfbSGavin Liu #define SOC_CHIP_ID U(0x8196) 125*a65fadfbSGavin Liu 126*a65fadfbSGavin Liu /******************************************************************************* 127*a65fadfbSGavin Liu * Platform memory map related constants 128*a65fadfbSGavin Liu ******************************************************************************/ 129*a65fadfbSGavin Liu #define TZRAM_BASE (0x94600000) 130*a65fadfbSGavin Liu #define TZRAM_SIZE (0x00200000) 131*a65fadfbSGavin Liu 132*a65fadfbSGavin Liu /******************************************************************************* 133*a65fadfbSGavin Liu * BL31 specific defines. 134*a65fadfbSGavin Liu ******************************************************************************/ 135*a65fadfbSGavin Liu /* 136*a65fadfbSGavin Liu * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 137*a65fadfbSGavin Liu * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 138*a65fadfbSGavin Liu * little space for growth. 139*a65fadfbSGavin Liu */ 140*a65fadfbSGavin Liu #define BL31_BASE (TZRAM_BASE + 0x1000) 141*a65fadfbSGavin Liu #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 142*a65fadfbSGavin Liu 143*a65fadfbSGavin Liu /******************************************************************************* 144*a65fadfbSGavin Liu * Platform specific page table and MMU setup constants 145*a65fadfbSGavin Liu ******************************************************************************/ 146*a65fadfbSGavin Liu #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39) 147*a65fadfbSGavin Liu #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39) 148*a65fadfbSGavin Liu #define MAX_XLAT_TABLES (128) 149*a65fadfbSGavin Liu #define MAX_MMAP_REGIONS (512) 150*a65fadfbSGavin Liu 151*a65fadfbSGavin Liu /******************************************************************************* 152*a65fadfbSGavin Liu * CPU PM definitions 153*a65fadfbSGavin Liu *******************************************************************************/ 154*a65fadfbSGavin Liu #define PLAT_CPU_PM_B_BUCK_ISO_ID (6) 155*a65fadfbSGavin Liu #define PLAT_CPU_PM_ILDO_ID (6) 156*a65fadfbSGavin Liu #define CPU_IDLE_SRAM_BASE (0x11B000) 157*a65fadfbSGavin Liu #define CPU_IDLE_SRAM_SIZE (0x1000) 158*a65fadfbSGavin Liu 159*a65fadfbSGavin Liu /******************************************************************************* 160*a65fadfbSGavin Liu * SYSTIMER related definitions 161*a65fadfbSGavin Liu ******************************************************************************/ 162*a65fadfbSGavin Liu #define SYSTIMER_BASE (0x1C400000) 163*a65fadfbSGavin Liu 164*a65fadfbSGavin Liu #endif /* PLATFORM_DEF_H */ 165