1 /* 2 * Copyright (c) 2024, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <platform_def.h> 9 #include <mtgpio.h> 10 11 typedef enum { 12 REG_0 = 0, 13 REG_1, 14 REG_2, 15 REG_3, 16 REG_4, 17 REG_5, 18 REG_6, 19 REG_7, 20 REG_8, 21 REG_9, 22 REG_10, 23 REG_11, 24 REG_12, 25 REG_13, 26 REG_14, 27 REG_15 28 } RegEnum; 29 30 uintptr_t mt_gpio_find_reg_addr(uint32_t pin) 31 { 32 uintptr_t reg_addr = 0U; 33 struct mt_pin_info gpio_info; 34 35 assert(pin < MAX_GPIO_PIN); 36 37 gpio_info = mt_pin_infos[pin]; 38 39 switch (gpio_info.base & 0xF) { 40 case REG_0: 41 reg_addr = GPIO_BASE; 42 break; 43 case REG_1: 44 reg_addr = IOCFG_RT_BASE; 45 break; 46 case REG_2: 47 reg_addr = IOCFG_RM1_BASE; 48 break; 49 case REG_3: 50 reg_addr = IOCFG_RM2_BASE; 51 break; 52 case REG_4: 53 reg_addr = IOCFG_RB_BASE; 54 break; 55 case REG_5: 56 reg_addr = IOCFG_BM1_BASE; 57 break; 58 case REG_6: 59 reg_addr = IOCFG_BM2_BASE; 60 break; 61 case REG_7: 62 reg_addr = IOCFG_BM3_BASE; 63 break; 64 case REG_8: 65 reg_addr = IOCFG_LT_BASE; 66 break; 67 case REG_9: 68 reg_addr = IOCFG_LM1_BASE; 69 break; 70 case REG_10: 71 reg_addr = IOCFG_LM2_BASE; 72 break; 73 case REG_11: 74 reg_addr = IOCFG_LB1_BASE; 75 break; 76 case REG_12: 77 reg_addr = IOCFG_LB2_BASE; 78 break; 79 case REG_13: 80 reg_addr = IOCFG_TM1_BASE; 81 break; 82 case REG_14: 83 reg_addr = IOCFG_TM2_BASE; 84 break; 85 case REG_15: 86 reg_addr = IOCFG_TM3_BASE; 87 break; 88 default: 89 break; 90 } 91 92 return reg_addr; 93 } 94