1*4cb9f2a5SCathy Xu /* 2*4cb9f2a5SCathy Xu * Copyright (c) 2024, MediaTek Inc. All rights reserved. 3*4cb9f2a5SCathy Xu * 4*4cb9f2a5SCathy Xu * SPDX-License-Identifier: BSD-3-Clause 5*4cb9f2a5SCathy Xu */ 6*4cb9f2a5SCathy Xu 7*4cb9f2a5SCathy Xu #include <assert.h> 8*4cb9f2a5SCathy Xu #include <platform_def.h> 9*4cb9f2a5SCathy Xu #include <mtgpio.h> 10*4cb9f2a5SCathy Xu 11*4cb9f2a5SCathy Xu typedef enum { 12*4cb9f2a5SCathy Xu REG_0 = 0, 13*4cb9f2a5SCathy Xu REG_1, 14*4cb9f2a5SCathy Xu REG_2, 15*4cb9f2a5SCathy Xu REG_3, 16*4cb9f2a5SCathy Xu REG_4, 17*4cb9f2a5SCathy Xu REG_5, 18*4cb9f2a5SCathy Xu REG_6, 19*4cb9f2a5SCathy Xu REG_7, 20*4cb9f2a5SCathy Xu REG_8, 21*4cb9f2a5SCathy Xu REG_9, 22*4cb9f2a5SCathy Xu REG_10, 23*4cb9f2a5SCathy Xu REG_11, 24*4cb9f2a5SCathy Xu REG_12, 25*4cb9f2a5SCathy Xu REG_13, 26*4cb9f2a5SCathy Xu REG_14 27*4cb9f2a5SCathy Xu } RegEnum; 28*4cb9f2a5SCathy Xu 29*4cb9f2a5SCathy Xu uintptr_t mt_gpio_find_reg_addr(uint32_t pin) 30*4cb9f2a5SCathy Xu { 31*4cb9f2a5SCathy Xu uintptr_t reg_addr = 0U; 32*4cb9f2a5SCathy Xu struct mt_pin_info gpio_info; 33*4cb9f2a5SCathy Xu 34*4cb9f2a5SCathy Xu assert(pin < MAX_GPIO_PIN); 35*4cb9f2a5SCathy Xu 36*4cb9f2a5SCathy Xu gpio_info = mt_pin_infos[pin]; 37*4cb9f2a5SCathy Xu 38*4cb9f2a5SCathy Xu switch (gpio_info.base & 0xF) { 39*4cb9f2a5SCathy Xu case REG_0: 40*4cb9f2a5SCathy Xu reg_addr = IOCFG_RT_BASE; 41*4cb9f2a5SCathy Xu break; 42*4cb9f2a5SCathy Xu case REG_1: 43*4cb9f2a5SCathy Xu reg_addr = IOCFG_RM1_BASE; 44*4cb9f2a5SCathy Xu break; 45*4cb9f2a5SCathy Xu case REG_2: 46*4cb9f2a5SCathy Xu reg_addr = IOCFG_RM2_BASE; 47*4cb9f2a5SCathy Xu break; 48*4cb9f2a5SCathy Xu case REG_3: 49*4cb9f2a5SCathy Xu reg_addr = IOCFG_RB_BASE; 50*4cb9f2a5SCathy Xu break; 51*4cb9f2a5SCathy Xu case REG_4: 52*4cb9f2a5SCathy Xu reg_addr = IOCFG_BM1_BASE; 53*4cb9f2a5SCathy Xu break; 54*4cb9f2a5SCathy Xu case REG_5: 55*4cb9f2a5SCathy Xu reg_addr = IOCFG_BM2_BASE; 56*4cb9f2a5SCathy Xu break; 57*4cb9f2a5SCathy Xu case REG_6: 58*4cb9f2a5SCathy Xu reg_addr = IOCFG_BM3_BASE; 59*4cb9f2a5SCathy Xu break; 60*4cb9f2a5SCathy Xu case REG_7: 61*4cb9f2a5SCathy Xu reg_addr = IOCFG_LT_BASE; 62*4cb9f2a5SCathy Xu break; 63*4cb9f2a5SCathy Xu case REG_8: 64*4cb9f2a5SCathy Xu reg_addr = IOCFG_LM1_BASE; 65*4cb9f2a5SCathy Xu break; 66*4cb9f2a5SCathy Xu case REG_9: 67*4cb9f2a5SCathy Xu reg_addr = IOCFG_LM2_BASE; 68*4cb9f2a5SCathy Xu break; 69*4cb9f2a5SCathy Xu case REG_10: 70*4cb9f2a5SCathy Xu reg_addr = IOCFG_LB1_BASE; 71*4cb9f2a5SCathy Xu break; 72*4cb9f2a5SCathy Xu case REG_11: 73*4cb9f2a5SCathy Xu reg_addr = IOCFG_LB2_BASE; 74*4cb9f2a5SCathy Xu break; 75*4cb9f2a5SCathy Xu case REG_12: 76*4cb9f2a5SCathy Xu reg_addr = IOCFG_TM1_BASE; 77*4cb9f2a5SCathy Xu break; 78*4cb9f2a5SCathy Xu case REG_13: 79*4cb9f2a5SCathy Xu reg_addr = IOCFG_TM2_BASE; 80*4cb9f2a5SCathy Xu break; 81*4cb9f2a5SCathy Xu case REG_14: 82*4cb9f2a5SCathy Xu reg_addr = IOCFG_TM3_BASE; 83*4cb9f2a5SCathy Xu break; 84*4cb9f2a5SCathy Xu default: 85*4cb9f2a5SCathy Xu break; 86*4cb9f2a5SCathy Xu } 87*4cb9f2a5SCathy Xu 88*4cb9f2a5SCathy Xu return reg_addr; 89*4cb9f2a5SCathy Xu } 90