14cb9f2a5SCathy Xu /*
24cb9f2a5SCathy Xu * Copyright (c) 2024, MediaTek Inc. All rights reserved.
34cb9f2a5SCathy Xu *
44cb9f2a5SCathy Xu * SPDX-License-Identifier: BSD-3-Clause
54cb9f2a5SCathy Xu */
64cb9f2a5SCathy Xu
74cb9f2a5SCathy Xu #include <assert.h>
84cb9f2a5SCathy Xu #include <platform_def.h>
94cb9f2a5SCathy Xu #include <mtgpio.h>
104cb9f2a5SCathy Xu
114cb9f2a5SCathy Xu typedef enum {
124cb9f2a5SCathy Xu REG_0 = 0,
134cb9f2a5SCathy Xu REG_1,
144cb9f2a5SCathy Xu REG_2,
154cb9f2a5SCathy Xu REG_3,
164cb9f2a5SCathy Xu REG_4,
174cb9f2a5SCathy Xu REG_5,
184cb9f2a5SCathy Xu REG_6,
194cb9f2a5SCathy Xu REG_7,
204cb9f2a5SCathy Xu REG_8,
214cb9f2a5SCathy Xu REG_9,
224cb9f2a5SCathy Xu REG_10,
234cb9f2a5SCathy Xu REG_11,
244cb9f2a5SCathy Xu REG_12,
254cb9f2a5SCathy Xu REG_13,
26*6f891e68SCathy Xu REG_14,
27*6f891e68SCathy Xu REG_15
284cb9f2a5SCathy Xu } RegEnum;
294cb9f2a5SCathy Xu
mt_gpio_find_reg_addr(uint32_t pin)304cb9f2a5SCathy Xu uintptr_t mt_gpio_find_reg_addr(uint32_t pin)
314cb9f2a5SCathy Xu {
324cb9f2a5SCathy Xu uintptr_t reg_addr = 0U;
334cb9f2a5SCathy Xu struct mt_pin_info gpio_info;
344cb9f2a5SCathy Xu
354cb9f2a5SCathy Xu assert(pin < MAX_GPIO_PIN);
364cb9f2a5SCathy Xu
374cb9f2a5SCathy Xu gpio_info = mt_pin_infos[pin];
384cb9f2a5SCathy Xu
394cb9f2a5SCathy Xu switch (gpio_info.base & 0xF) {
404cb9f2a5SCathy Xu case REG_0:
41*6f891e68SCathy Xu reg_addr = GPIO_BASE;
424cb9f2a5SCathy Xu break;
434cb9f2a5SCathy Xu case REG_1:
44*6f891e68SCathy Xu reg_addr = IOCFG_RT_BASE;
454cb9f2a5SCathy Xu break;
464cb9f2a5SCathy Xu case REG_2:
47*6f891e68SCathy Xu reg_addr = IOCFG_RM1_BASE;
484cb9f2a5SCathy Xu break;
494cb9f2a5SCathy Xu case REG_3:
50*6f891e68SCathy Xu reg_addr = IOCFG_RM2_BASE;
514cb9f2a5SCathy Xu break;
524cb9f2a5SCathy Xu case REG_4:
53*6f891e68SCathy Xu reg_addr = IOCFG_RB_BASE;
544cb9f2a5SCathy Xu break;
554cb9f2a5SCathy Xu case REG_5:
56*6f891e68SCathy Xu reg_addr = IOCFG_BM1_BASE;
574cb9f2a5SCathy Xu break;
584cb9f2a5SCathy Xu case REG_6:
59*6f891e68SCathy Xu reg_addr = IOCFG_BM2_BASE;
604cb9f2a5SCathy Xu break;
614cb9f2a5SCathy Xu case REG_7:
62*6f891e68SCathy Xu reg_addr = IOCFG_BM3_BASE;
634cb9f2a5SCathy Xu break;
644cb9f2a5SCathy Xu case REG_8:
65*6f891e68SCathy Xu reg_addr = IOCFG_LT_BASE;
664cb9f2a5SCathy Xu break;
674cb9f2a5SCathy Xu case REG_9:
68*6f891e68SCathy Xu reg_addr = IOCFG_LM1_BASE;
694cb9f2a5SCathy Xu break;
704cb9f2a5SCathy Xu case REG_10:
71*6f891e68SCathy Xu reg_addr = IOCFG_LM2_BASE;
724cb9f2a5SCathy Xu break;
734cb9f2a5SCathy Xu case REG_11:
74*6f891e68SCathy Xu reg_addr = IOCFG_LB1_BASE;
754cb9f2a5SCathy Xu break;
764cb9f2a5SCathy Xu case REG_12:
77*6f891e68SCathy Xu reg_addr = IOCFG_LB2_BASE;
784cb9f2a5SCathy Xu break;
794cb9f2a5SCathy Xu case REG_13:
80*6f891e68SCathy Xu reg_addr = IOCFG_TM1_BASE;
814cb9f2a5SCathy Xu break;
824cb9f2a5SCathy Xu case REG_14:
83*6f891e68SCathy Xu reg_addr = IOCFG_TM2_BASE;
84*6f891e68SCathy Xu break;
85*6f891e68SCathy Xu case REG_15:
864cb9f2a5SCathy Xu reg_addr = IOCFG_TM3_BASE;
874cb9f2a5SCathy Xu break;
884cb9f2a5SCathy Xu default:
894cb9f2a5SCathy Xu break;
904cb9f2a5SCathy Xu }
914cb9f2a5SCathy Xu
924cb9f2a5SCathy Xu return reg_addr;
934cb9f2a5SCathy Xu }
94