1 /* 2 * Copyright (c) 2025, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef DCM_MTK_DCM_UTILS_H_ 8 #define DCM_MTK_DCM_UTILS_H_ 9 10 #include <stdbool.h> 11 12 #include <platform_def.h> 13 14 #define MCUSYS_PAR_WRAP_BASE (MCUCFG_BASE + 0x001B0000) 15 #define MCUSYS_PAR_WRAP_SIZE (0x10000) 16 #define APINFRA_IO_CTRL_AO (IO_PHYS + 0x00156000) 17 #define APINFRA_IO_CTRL_AO_SIZE (0x1000) 18 #define APINFRA_IO_NOC_AO (IO_PHYS + 0x04012000) 19 #define APINFRA_IO_NOC_AO_SIZE (0x1000) 20 #define APINFRA_MEM_INTF_NOC_AO (IO_PHYS + 0x04032000) 21 #define APINFRA_MEM_INTF_NOC_AO_SIZE (0x1000) 22 #define APINFRA_MEM_CTRL_AO (IO_PHYS + 0x04124000) 23 #define APINFRA_MEM_CTRL_AO_SIZE (0x1000) 24 #define PERI_AO_BCRM_BASE (IO_PHYS + 0x06610000) 25 #define PERI_AO_BCRM_BASE_SIZE (0x1000) 26 #define VLP_AO_BCRM_BASE (IO_PHYS + 0x0c030000) 27 #define VLP_AO_BCRM_BASE_SIZE (0x1000) 28 29 #define MCUSYS_PAR_WRAP_L3_SHARE_DCM_CTRL (MCUSYS_PAR_WRAP_BASE + 0x78) 30 #define MCUSYS_PAR_WRAP_MP_ADB_DCM_CFG0 (MCUSYS_PAR_WRAP_BASE + 0x270) 31 #define MCUSYS_PAR_WRAP_ADB_FIFO_DCM_EN (MCUSYS_PAR_WRAP_BASE + 0x278) 32 #define MCUSYS_PAR_WRAP_MP0_DCM_CFG0 (MCUSYS_PAR_WRAP_BASE + 0x27c) 33 #define MCUSYS_PAR_WRAP_QDCM_CONFIG0 (MCUSYS_PAR_WRAP_BASE + 0x280) 34 #define MCUSYS_PAR_WRAP_L3GIC_ARCH_CG_CONFIG (MCUSYS_PAR_WRAP_BASE + 0x294) 35 #define MCUSYS_PAR_WRAP_QDCM_CONFIG1 (MCUSYS_PAR_WRAP_BASE + 0x284) 36 #define MCUSYS_PAR_WRAP_QDCM_CONFIG2 (MCUSYS_PAR_WRAP_BASE + 0x288) 37 #define MCUSYS_PAR_WRAP_QDCM_CONFIG3 (MCUSYS_PAR_WRAP_BASE + 0x28c) 38 #define MCUSYS_PAR_WRAP_CI700_DCM_CTRL (MCUSYS_PAR_WRAP_BASE + 0x298) 39 #define MCUSYS_PAR_WRAP_CBIP_CABGEN_3TO1_CONFIG (MCUSYS_PAR_WRAP_BASE + 0x2a0) 40 #define MCUSYS_PAR_WRAP_CBIP_CABGEN_2TO1_CONFIG (MCUSYS_PAR_WRAP_BASE + 0x2a4) 41 #define MCUSYS_PAR_WRAP_CBIP_CABGEN_4TO2_CONFIG (MCUSYS_PAR_WRAP_BASE + 0x2a8) 42 #define MCUSYS_PAR_WRAP_CBIP_CABGEN_1TO2_CONFIG (MCUSYS_PAR_WRAP_BASE + 0x2ac) 43 #define MCUSYS_PAR_WRAP_CBIP_CABGEN_2TO5_CONFIG (MCUSYS_PAR_WRAP_BASE + 0x2b0) 44 #define MCUSYS_PAR_WRAP_CBIP_P2P_CONFIG0 (MCUSYS_PAR_WRAP_BASE + 0x2b4) 45 #define MCUSYS_PAR_WRAP_CBIP_CABGEN_1TO2_L3GIC_CONFIG \ 46 (MCUSYS_PAR_WRAP_BASE + 0x2bc) 47 #define MCUSYS_PAR_WRAP_CBIP_CABGEN_1TO2_INFRA_CONFIG \ 48 (MCUSYS_PAR_WRAP_BASE + 0x2c4) 49 #define MCUSYS_PAR_WRAP_MP_CENTRAL_FABRIC_SUB_CHANNEL_CG \ 50 (MCUSYS_PAR_WRAP_BASE + 0x2b8) 51 #define MCUSYS_PAR_WRAP_ACP_SLAVE_DCM_EN (MCUSYS_PAR_WRAP_BASE + 0x2dc) 52 #define MCUSYS_PAR_WRAP_GIC_SPI_SLOW_CK_CFG (MCUSYS_PAR_WRAP_BASE + 0x2e0) 53 #define MCUSYS_PAR_WRAP_EBG_CKE_WRAP_FIFO_CFG (MCUSYS_PAR_WRAP_BASE + 0x404) 54 #define CLK_AXI_VDNR_DCM_TOP_APINFRA_IO_INTX_BUS_CTRL_0 \ 55 (APINFRA_IO_CTRL_AO + 0x8) 56 #define CLK_IO_NOC_VDNR_DCM_TOP_APINFRA_IO_INTF_PAR_BUS_CTRL_0 \ 57 (APINFRA_IO_NOC_AO + 0x4) 58 #define VDNR_DCM_TOP_APINFRA_MEM_INTF_PAR_BUS_CTRL_0 \ 59 (APINFRA_MEM_INTF_NOC_AO + 0x0) 60 #define CLK_FMEM_SUB_CFG_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_0 \ 61 (APINFRA_MEM_CTRL_AO + 0xc) 62 #define CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_0 \ 63 (APINFRA_MEM_CTRL_AO + 0x14) 64 #define CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_1 \ 65 (APINFRA_MEM_CTRL_AO + 0x18) 66 #define CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_2 \ 67 (APINFRA_MEM_CTRL_AO + 0x1c) 68 #define CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_3 \ 69 (APINFRA_MEM_CTRL_AO + 0x20) 70 #define CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_4 \ 71 (APINFRA_MEM_CTRL_AO + 0x24) 72 #define CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_5 \ 73 (APINFRA_MEM_CTRL_AO + 0x28) 74 75 #define VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_0 (PERI_AO_BCRM_BASE + 0x2c) 76 #define VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_1 (PERI_AO_BCRM_BASE + 0x30) 77 #define VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_2 (PERI_AO_BCRM_BASE + 0x34) 78 #define VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_3 (PERI_AO_BCRM_BASE + 0x38) 79 #define VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_0 (PERI_AO_BCRM_BASE + 0x20) 80 #define VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_1 (PERI_AO_BCRM_BASE + 0x24) 81 #define VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_2 (PERI_AO_BCRM_BASE + 0x28) 82 #define VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_3 (PERI_AO_BCRM_BASE + 0x2c) 83 #define VDNR_DCM_TOP_VLP_PAR_BUS_TOP_CTRL_0 (VLP_AO_BCRM_BASE + 0x5c) 84 85 #define MCUSYS_PAR_WRAP_MCU_L3C_DCM_REG0_MASK 0x1 86 #define MCUSYS_PAR_WRAP_MCU_L3C_DCM_REG0_ON 0x1 87 #define MCUSYS_PAR_WRAP_MCU_L3C_DCM_REG0_OFF 0 88 #define MCUSYS_PAR_WRAP_MCU_ACP_DCM_REG0_MASK 0x10001 89 #define MCUSYS_PAR_WRAP_MCU_ACP_DCM_REG0_ON 0x10001 90 #define MCUSYS_PAR_WRAP_MCU_ACP_DCM_REG0_OFF 0 91 #define MCUSYS_PAR_WRAP_MCU_ADB_DCM_REG0_MASK 0x1FFF07FF 92 #define MCUSYS_PAR_WRAP_MCU_ADB_DCM_REG0_ON 0x1FFF07FF 93 #define MCUSYS_PAR_WRAP_MCU_ADB_DCM_REG0_OFF 0 94 #define MCUSYS_PAR_WRAP_MCU_STALLDCM_REG0_MASK 0xFF 95 #define MCUSYS_PAR_WRAP_MCU_STALLDCM_REG0_ON 0xFF 96 #define MCUSYS_PAR_WRAP_MCU_STALLDCM_REG0_OFF 0 97 #define MCUSYS_PAR_WRAP_MCU_APB_DCM_REG0_MASK 0x1FFFF00 98 #define MCUSYS_PAR_WRAP_MCU_APB_DCM_REG0_ON 0x1FFFF00 99 #define MCUSYS_PAR_WRAP_MCU_APB_DCM_REG0_OFF 0 100 #define MCUSYS_PAR_WRAP_MCU_IO_DCM_REG0_MASK 0x1001 101 #define MCUSYS_PAR_WRAP_MCU_IO_DCM_REG1_MASK 0x1 102 #define MCUSYS_PAR_WRAP_MCU_IO_DCM_REG0_ON 0x1001 103 #define MCUSYS_PAR_WRAP_MCU_IO_DCM_REG1_ON 0x1 104 #define MCUSYS_PAR_WRAP_MCU_IO_DCM_REG0_OFF 0 105 #define MCUSYS_PAR_WRAP_MCU_IO_DCM_REG1_OFF 0 106 #define MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG0_MASK 0x1110000 107 #define MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG1_MASK 0x1111 108 #define MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG0_ON 0x1110000 109 #define MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG1_ON 0x1111 110 #define MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG0_OFF 0 111 #define MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG1_OFF 0 112 #define MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG0_MASK 0x11111111 113 #define MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG1_MASK 0x1111 114 #define MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG0_ON 0x11111111 115 #define MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG1_ON 0x1111 116 #define MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG0_OFF 0 117 #define MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG1_OFF 0 118 #define MCUSYS_PAR_WRAP_MCU_BKR_LDCM1_REG0_MASK 0XFFFF0003 119 #define MCUSYS_PAR_WRAP_MCU_BKR_LDCM1_REG0_ON 0x8A080002 120 #define MCUSYS_PAR_WRAP_MCU_BKR_LDCM1_REG0_OFF 0x8A080000 121 #define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG0_MASK 0x1 122 #define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG1_MASK 0x3 123 #define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG2_MASK 0x1 124 #define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG3_MASK 0x1 125 #define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG4_MASK 0x1 126 #define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG5_MASK 0x7 127 #define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG6_MASK 0x1 128 #define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG7_MASK 0x1 129 #define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG0_ON 0 130 #define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG1_ON 0 131 #define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG2_ON 0 132 #define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG3_ON 0 133 #define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG4_ON 0 134 #define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG5_ON 0x7 135 #define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG6_ON 0 136 #define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG7_ON 0 137 #define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG0_OFF 0x1 138 #define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG1_OFF 0x3 139 #define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG2_OFF 0x1 140 #define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG3_OFF 0x1 141 #define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG4_OFF 0x1 142 #define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG5_OFF 0 143 #define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG6_OFF 0x1 144 #define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG7_OFF 0x1 145 #define MCUSYS_PAR_WRAP_MCU_MISC_DCM_REG0_MASK 0x1 146 #define MCUSYS_PAR_WRAP_MCU_MISC_DCM_REG0_ON 0x1 147 #define MCUSYS_PAR_WRAP_MCU_MISC_DCM_REG0_OFF 0 148 #define MCUSYS_PAR_WRAP_MCU_DSU_ACP_DCM_REG0_MASK 0x1 149 #define MCUSYS_PAR_WRAP_MCU_DSU_ACP_DCM_REG0_ON 0x1 150 #define MCUSYS_PAR_WRAP_MCU_DSU_ACP_DCM_REG0_OFF 0 151 #define MCUSYS_PAR_WRAP_MCU_CHI_MON_DCM_REG0_MASK 0x1E 152 #define MCUSYS_PAR_WRAP_MCU_CHI_MON_DCM_REG0_ON 0 153 #define MCUSYS_PAR_WRAP_MCU_CHI_MON_DCM_REG0_OFF 0x1E 154 #define MCUSYS_PAR_WRAP_MCU_GIC_SPI_DCM_REG0_MASK 0x1 155 #define MCUSYS_PAR_WRAP_MCU_GIC_SPI_DCM_REG0_ON 0x1 156 #define MCUSYS_PAR_WRAP_MCU_GIC_SPI_DCM_REG0_OFF 0 157 #define MCUSYS_PAR_WRAP_MCU_EBG_DCM_REG0_MASK BIT(2) 158 #define MCUSYS_PAR_WRAP_MCU_EBG_DCM_REG0_ON 0 159 #define MCUSYS_PAR_WRAP_MCU_EBG_DCM_REG0_OFF BIT(2) 160 #define APINFRA_IO_CTRL_AO_INFRA_BUS_DCM_REG0_MASK 0x14 161 #define APINFRA_IO_CTRL_AO_INFRA_BUS_DCM_REG0_ON 0x14 162 #define APINFRA_IO_CTRL_AO_INFRA_BUS_DCM_REG0_OFF 0 163 #define APINFRA_IO_NOC_AO_INFRA_BUS_DCM_REG0_MASK BIT(4) 164 #define APINFRA_IO_NOC_AO_INFRA_BUS_DCM_REG0_ON BIT(4) 165 #define APINFRA_IO_NOC_AO_INFRA_BUS_DCM_REG0_OFF 0 166 #define APINFRA_MEM_INTF_NOC_AO_INFRA_BUS_DCM_REG0_MASK BIT(4) 167 #define APINFRA_MEM_INTF_NOC_AO_INFRA_BUS_DCM_REG0_ON BIT(4) 168 #define APINFRA_MEM_INTF_NOC_AO_INFRA_BUS_DCM_REG0_OFF 0 169 #define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG0_MASK 0x1C 170 #define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG1_MASK 0x90 171 #define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG2_MASK BIT(21) 172 #define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG3_MASK BIT(22) 173 #define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG4_MASK BIT(20) 174 #define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG5_MASK BIT(24) 175 #define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG6_MASK BIT(23) 176 #define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG0_ON 0x1C 177 #define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG1_ON 0x90 178 #define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG2_ON BIT(21) 179 #define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG3_ON BIT(22) 180 #define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG4_ON BIT(20) 181 #define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG5_ON BIT(24) 182 #define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG6_ON BIT(23) 183 #define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG0_OFF 0 184 #define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG1_OFF 0 185 #define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG2_OFF 0 186 #define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG3_OFF 0 187 #define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG4_OFF 0 188 #define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG5_OFF 0 189 #define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG6_OFF 0 190 #define PERI_AO_BCRM_PERI_BUS_DCM_REG0_MASK 0x14920 191 #define PERI_AO_BCRM_PERI_BUS_DCM_REG1_MASK BIT(13) 192 #define PERI_AO_BCRM_PERI_BUS_DCM_REG2_MASK BIT(13) 193 #define PERI_AO_BCRM_PERI_BUS_DCM_REG3_MASK BIT(13) 194 #define PERI_AO_BCRM_PERI_BUS_DCM_REG0_ON 0x14920 195 #define PERI_AO_BCRM_PERI_BUS_DCM_REG1_ON BIT(13) 196 #define PERI_AO_BCRM_PERI_BUS_DCM_REG2_ON BIT(13) 197 #define PERI_AO_BCRM_PERI_BUS_DCM_REG3_ON BIT(13) 198 #define PERI_AO_BCRM_PERI_BUS_DCM_REG0_OFF 0 199 #define PERI_AO_BCRM_PERI_BUS_DCM_REG1_OFF 0 200 #define PERI_AO_BCRM_PERI_BUS_DCM_REG2_OFF 0 201 #define PERI_AO_BCRM_PERI_BUS_DCM_REG3_OFF 0 202 #define VLP_AO_BCRM_VLP_BUS_DCM_REG0_MASK 0x7C026 203 #define VLP_AO_BCRM_VLP_BUS_DCM_REG0_ON 0x26 204 #define VLP_AO_BCRM_VLP_BUS_DCM_REG0_OFF 0x6 205 #define MCUSYS_PAR_WRAP_MCU_BKR_LDCM2_REG0_MASK (0xFFFF0003) 206 #define MCUSYS_PAR_WRAP_MCU_BKR_LDCM2_REG0_ON (0x8A080003) 207 #define MCUSYS_PAR_WRAP_MCU_BKR_LDCM2_REG0_OFF (0xA0880000) 208 209 void dcm_mcusys_par_wrap_mcu_l3c_dcm(bool on); 210 bool dcm_mcusys_par_wrap_mcu_l3c_dcm_is_on(void); 211 void dcm_mcusys_par_wrap_mcu_acp_dcm(bool on); 212 bool dcm_mcusys_par_wrap_mcu_acp_dcm_is_on(void); 213 void dcm_mcusys_par_wrap_mcu_adb_dcm(bool on); 214 bool dcm_mcusys_par_wrap_mcu_adb_dcm_is_on(void); 215 void dcm_mcusys_par_wrap_mcu_stalldcm(bool on); 216 bool dcm_mcusys_par_wrap_mcu_stalldcm_is_on(void); 217 void dcm_mcusys_par_wrap_mcu_apb_dcm(bool on); 218 bool dcm_mcusys_par_wrap_mcu_apb_dcm_is_on(void); 219 void dcm_mcusys_par_wrap_mcu_io_dcm(bool on); 220 bool dcm_mcusys_par_wrap_mcu_io_dcm_is_on(void); 221 void dcm_mcusys_par_wrap_mcu_bus_qdcm(bool on); 222 bool dcm_mcusys_par_wrap_mcu_bus_qdcm_is_on(void); 223 void dcm_mcusys_par_wrap_mcu_core_qdcm(bool on); 224 bool dcm_mcusys_par_wrap_mcu_core_qdcm_is_on(void); 225 void dcm_mcusys_par_wrap_mcu_bkr_ldcm1(bool on); 226 bool dcm_mcusys_par_wrap_mcu_bkr_ldcm1_is_on(void); 227 void dcm_mcusys_par_wrap_mcu_bkr_ldcm2(bool on); 228 bool dcm_mcusys_par_wrap_mcu_bkr_ldcm2_is_on(void); 229 void dcm_mcusys_par_wrap_mcu_cbip_dcm(bool on); 230 bool dcm_mcusys_par_wrap_mcu_cbip_dcm_is_on(void); 231 void dcm_mcusys_par_wrap_mcu_misc_dcm(bool on); 232 bool dcm_mcusys_par_wrap_mcu_misc_dcm_is_on(void); 233 void dcm_mcusys_par_wrap_mcu_dsu_acp_dcm(bool on); 234 bool dcm_mcusys_par_wrap_mcu_dsu_acp_dcm_is_on(void); 235 void dcm_mcusys_par_wrap_mcu_chi_mon_dcm(bool on); 236 bool dcm_mcusys_par_wrap_mcu_chi_mon_dcm_is_on(void); 237 void dcm_mcusys_par_wrap_mcu_gic_spi_dcm(bool on); 238 bool dcm_mcusys_par_wrap_mcu_gic_spi_dcm_is_on(void); 239 void dcm_mcusys_par_wrap_mcu_ebg_dcm(bool on); 240 bool dcm_mcusys_par_wrap_mcu_ebg_dcm_is_on(void); 241 void dcm_bcrm_apinfra_io_ctrl_ao_infra_bus_dcm(bool on); 242 bool dcm_bcrm_apinfra_io_ctrl_ao_infra_bus_dcm_is_on(void); 243 void dcm_bcrm_apinfra_io_noc_ao_infra_bus_dcm(bool on); 244 bool dcm_bcrm_apinfra_io_noc_ao_infra_bus_dcm_is_on(void); 245 void dcm_bcrm_apinfra_mem_intf_noc_ao_infra_bus_dcm(bool on); 246 bool dcm_bcrm_apinfra_mem_intf_noc_ao_infra_bus_dcm_is_on(void); 247 void dcm_bcrm_apinfra_mem_ctrl_ao_infra_bus_dcm(bool on); 248 bool dcm_bcrm_apinfra_mem_ctrl_ao_infra_bus_dcm_is_on(void); 249 void dcm_peri_ao_bcrm_peri_bus1_dcm(bool on); 250 bool dcm_peri_ao_bcrm_peri_bus1_dcm_is_on(void); 251 void dcm_peri_ao_bcrm_peri_bus2_dcm(bool on); 252 bool dcm_peri_ao_bcrm_peri_bus2_dcm_is_on(void); 253 void dcm_vlp_ao_bcrm_vlp_bus_dcm(bool on); 254 bool dcm_vlp_ao_bcrm_vlp_bus_dcm_is_on(void); 255 256 #endif /* DCM_MTK_DCM_UTILS_H_ */ 257