1*174a1cfeSYidi Lin /* 2*174a1cfeSYidi Lin * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. 3*174a1cfeSYidi Lin * 4*174a1cfeSYidi Lin * SPDX-License-Identifier: BSD-3-Clause 5*174a1cfeSYidi Lin */ 6*174a1cfeSYidi Lin 7*174a1cfeSYidi Lin #include <arch.h> 8*174a1cfeSYidi Lin #include <arch_helpers.h> 9*174a1cfeSYidi Lin #include <lib/psci/psci.h> 10*174a1cfeSYidi Lin 11*174a1cfeSYidi Lin #include <plat_helpers.h> 12*174a1cfeSYidi Lin #include <platform_def.h> 13*174a1cfeSYidi Lin 14*174a1cfeSYidi Lin const unsigned char mtk_power_domain_tree_desc[] = { 15*174a1cfeSYidi Lin /* Number of root nodes */ 16*174a1cfeSYidi Lin PLATFORM_SYSTEM_COUNT, 17*174a1cfeSYidi Lin /* Number of children for the root node */ 18*174a1cfeSYidi Lin PLATFORM_MCUSYS_COUNT, 19*174a1cfeSYidi Lin /* Number of children for the mcusys node */ 20*174a1cfeSYidi Lin PLATFORM_CLUSTER_COUNT, 21*174a1cfeSYidi Lin /* Number of children for the first cluster node */ 22*174a1cfeSYidi Lin PLATFORM_CLUSTER0_CORE_COUNT, 23*174a1cfeSYidi Lin }; 24*174a1cfeSYidi Lin 25*174a1cfeSYidi Lin const unsigned char *plat_get_power_domain_tree_desc(void) 26*174a1cfeSYidi Lin { 27*174a1cfeSYidi Lin return mtk_power_domain_tree_desc; 28*174a1cfeSYidi Lin } 29*174a1cfeSYidi Lin 30*174a1cfeSYidi Lin /******************************************************************************* 31*174a1cfeSYidi Lin * This function implements a part of the critical interface between the psci 32*174a1cfeSYidi Lin * generic layer and the platform that allows the former to query the platform 33*174a1cfeSYidi Lin * to convert an MPIDR to a unique linear index. An error code (-1) is returned 34*174a1cfeSYidi Lin * in case the MPIDR is invalid. 35*174a1cfeSYidi Lin ******************************************************************************/ 36*174a1cfeSYidi Lin int plat_core_pos_by_mpidr(u_register_t mpidr) 37*174a1cfeSYidi Lin { 38*174a1cfeSYidi Lin unsigned int cluster_id, cpu_id; 39*174a1cfeSYidi Lin 40*174a1cfeSYidi Lin if ((read_mpidr() & MPIDR_MT_MASK) != 0) { 41*174a1cfeSYidi Lin /* ARMv8.2 arch */ 42*174a1cfeSYidi Lin if ((mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) != 0) { 43*174a1cfeSYidi Lin return -1; 44*174a1cfeSYidi Lin } 45*174a1cfeSYidi Lin return plat_mediatek_calc_core_pos(mpidr); 46*174a1cfeSYidi Lin } 47*174a1cfeSYidi Lin 48*174a1cfeSYidi Lin mpidr &= MPIDR_AFFINITY_MASK; 49*174a1cfeSYidi Lin 50*174a1cfeSYidi Lin if ((mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) != 0) { 51*174a1cfeSYidi Lin return -1; 52*174a1cfeSYidi Lin } 53*174a1cfeSYidi Lin 54*174a1cfeSYidi Lin cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; 55*174a1cfeSYidi Lin cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; 56*174a1cfeSYidi Lin 57*174a1cfeSYidi Lin if (cluster_id >= PLATFORM_CLUSTER_COUNT) { 58*174a1cfeSYidi Lin return -1; 59*174a1cfeSYidi Lin } 60*174a1cfeSYidi Lin 61*174a1cfeSYidi Lin /* 62*174a1cfeSYidi Lin * Validate cpu_id by checking whether it represents a CPU in 63*174a1cfeSYidi Lin * one of the two clusters present on the platform. 64*174a1cfeSYidi Lin */ 65*174a1cfeSYidi Lin if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) { 66*174a1cfeSYidi Lin return -1; 67*174a1cfeSYidi Lin } 68*174a1cfeSYidi Lin 69*174a1cfeSYidi Lin return (cpu_id + (cluster_id * 8)); 70*174a1cfeSYidi Lin } 71