1 /* 2 * Copyright (c) 2021, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* common headers */ 8 #include <assert.h> 9 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <drivers/gpio.h> 13 #include <lib/psci/psci.h> 14 15 /* platform specific headers */ 16 #include <mt_gic_v3.h> 17 #include <mtspmc.h> 18 #include <plat/common/platform.h> 19 #include <plat_mtk_lpm.h> 20 #include <plat_params.h> 21 #include <plat_pm.h> 22 #include <pmic.h> 23 #include <rtc.h> 24 25 /* 26 * Cluster state request: 27 * [0] : The CPU requires cluster power down 28 * [1] : The CPU requires cluster power on 29 */ 30 #define coordinate_cluster(onoff) write_clusterpwrdn_el1(onoff) 31 #define coordinate_cluster_pwron() coordinate_cluster(1) 32 #define coordinate_cluster_pwroff() coordinate_cluster(0) 33 34 /* platform secure entry point */ 35 static uintptr_t secure_entrypoint; 36 /* per-CPU power state */ 37 static unsigned int plat_power_state[PLATFORM_CORE_COUNT]; 38 39 /* platform CPU power domain - ops */ 40 static const struct mt_lpm_tz *plat_mt_pm; 41 42 #define plat_mt_pm_invoke(_name, _cpu, _state) ({ \ 43 int ret = -1; \ 44 if (plat_mt_pm != NULL && plat_mt_pm->_name != NULL) { \ 45 ret = plat_mt_pm->_name(_cpu, _state); \ 46 } \ 47 ret; }) 48 49 #define plat_mt_pm_invoke_no_check(_name, _cpu, _state) ({ \ 50 if (plat_mt_pm != NULL && plat_mt_pm->_name != NULL) { \ 51 (void) plat_mt_pm->_name(_cpu, _state); \ 52 } \ 53 }) 54 55 /* 56 * Common MTK_platform operations to power on/off a 57 * CPU in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request. 58 */ 59 60 static void plat_cpu_pwrdwn_common(unsigned int cpu, 61 const psci_power_state_t *state, unsigned int req_pstate) 62 { 63 assert(cpu == plat_my_core_pos()); 64 65 plat_mt_pm_invoke_no_check(pwr_cpu_dwn, cpu, state); 66 67 if ((psci_get_pstate_pwrlvl(req_pstate) >= MTK_AFFLVL_CLUSTER) || 68 (req_pstate == 0U)) { /* hotplug off */ 69 coordinate_cluster_pwroff(); 70 } 71 72 /* Prevent interrupts from spuriously waking up this CPU */ 73 mt_gic_rdistif_save(); 74 gicv3_cpuif_disable(cpu); 75 gicv3_rdistif_off(cpu); 76 } 77 78 static void plat_cpu_pwron_common(unsigned int cpu, 79 const psci_power_state_t *state, unsigned int req_pstate) 80 { 81 assert(cpu == plat_my_core_pos()); 82 83 plat_mt_pm_invoke_no_check(pwr_cpu_on, cpu, state); 84 85 coordinate_cluster_pwron(); 86 87 /* Enable the GIC CPU interface */ 88 gicv3_rdistif_on(cpu); 89 gicv3_cpuif_enable(cpu); 90 mt_gic_rdistif_init(); 91 92 /* 93 * If mcusys does power down before then restore 94 * all CPUs' GIC Redistributors 95 */ 96 if (IS_MCUSYS_OFF_STATE(state)) { 97 mt_gic_rdistif_restore_all(); 98 } else { 99 mt_gic_rdistif_restore(); 100 } 101 } 102 103 /* 104 * Common MTK_platform operations to power on/off a 105 * cluster in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request. 106 */ 107 108 static void plat_cluster_pwrdwn_common(unsigned int cpu, 109 const psci_power_state_t *state, unsigned int req_pstate) 110 { 111 assert(cpu == plat_my_core_pos()); 112 113 if (plat_mt_pm_invoke(pwr_cluster_dwn, cpu, state) != 0) { 114 coordinate_cluster_pwron(); 115 116 /* TODO: return on fail. 117 * Add a 'return' here before adding any code following 118 * the if-block. 119 */ 120 } 121 } 122 123 static void plat_cluster_pwron_common(unsigned int cpu, 124 const psci_power_state_t *state, unsigned int req_pstate) 125 { 126 assert(cpu == plat_my_core_pos()); 127 128 if (plat_mt_pm_invoke(pwr_cluster_on, cpu, state) != 0) { 129 /* TODO: return on fail. 130 * Add a 'return' here before adding any code following 131 * the if-block. 132 */ 133 } 134 } 135 136 /* 137 * Common MTK_platform operations to power on/off a 138 * mcusys in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request. 139 */ 140 141 static void plat_mcusys_pwrdwn_common(unsigned int cpu, 142 const psci_power_state_t *state, unsigned int req_pstate) 143 { 144 assert(cpu == plat_my_core_pos()); 145 146 if (plat_mt_pm_invoke(pwr_mcusys_dwn, cpu, state) != 0) { 147 return; /* return on fail */ 148 } 149 150 mt_gic_distif_save(); 151 gic_sgi_save_all(); 152 } 153 154 static void plat_mcusys_pwron_common(unsigned int cpu, 155 const psci_power_state_t *state, unsigned int req_pstate) 156 { 157 assert(cpu == plat_my_core_pos()); 158 159 if (plat_mt_pm_invoke(pwr_mcusys_on, cpu, state) != 0) { 160 return; /* return on fail */ 161 } 162 163 mt_gic_init(); 164 mt_gic_distif_restore(); 165 gic_sgi_restore_all(); 166 167 plat_mt_pm_invoke_no_check(pwr_mcusys_on_finished, cpu, state); 168 } 169 170 /* 171 * plat_psci_ops implementation 172 */ 173 174 static void plat_cpu_standby(plat_local_state_t cpu_state) 175 { 176 uint64_t scr; 177 178 scr = read_scr_el3(); 179 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); 180 181 isb(); 182 dsb(); 183 wfi(); 184 185 write_scr_el3(scr); 186 } 187 188 static int plat_power_domain_on(u_register_t mpidr) 189 { 190 unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr); 191 unsigned int cluster = 0U; 192 193 if (cpu >= PLATFORM_CORE_COUNT) { 194 return PSCI_E_INVALID_PARAMS; 195 } 196 197 if (!spm_get_cluster_powerstate(cluster)) { 198 spm_poweron_cluster(cluster); 199 } 200 201 /* init CPU reset arch as AARCH64 */ 202 mcucfg_init_archstate(cluster, cpu, true); 203 mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint); 204 spm_poweron_cpu(cluster, cpu); 205 206 return PSCI_E_SUCCESS; 207 } 208 209 static void plat_power_domain_on_finish(const psci_power_state_t *state) 210 { 211 unsigned long mpidr = read_mpidr_el1(); 212 unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr); 213 214 assert(cpu < PLATFORM_CORE_COUNT); 215 216 /* Allow IRQs to wakeup this core in IDLE flow */ 217 mcucfg_enable_gic_wakeup(0U, cpu); 218 219 if (IS_CLUSTER_OFF_STATE(state)) { 220 plat_cluster_pwron_common(cpu, state, 0U); 221 } 222 223 plat_cpu_pwron_common(cpu, state, 0U); 224 } 225 226 static void plat_power_domain_off(const psci_power_state_t *state) 227 { 228 unsigned long mpidr = read_mpidr_el1(); 229 unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr); 230 231 assert(cpu < PLATFORM_CORE_COUNT); 232 233 plat_cpu_pwrdwn_common(cpu, state, 0U); 234 spm_poweroff_cpu(0U, cpu); 235 236 /* prevent unintended IRQs from waking up the hot-unplugged core */ 237 mcucfg_disable_gic_wakeup(0U, cpu); 238 239 if (IS_CLUSTER_OFF_STATE(state)) { 240 plat_cluster_pwrdwn_common(cpu, state, 0U); 241 } 242 } 243 244 static void plat_power_domain_suspend(const psci_power_state_t *state) 245 { 246 unsigned int cpu = plat_my_core_pos(); 247 248 assert(cpu < PLATFORM_CORE_COUNT); 249 250 plat_mt_pm_invoke_no_check(pwr_prompt, cpu, state); 251 252 /* Perform the common CPU specific operations */ 253 plat_cpu_pwrdwn_common(cpu, state, plat_power_state[cpu]); 254 255 if (IS_CLUSTER_OFF_STATE(state)) { 256 /* Perform the common cluster specific operations */ 257 plat_cluster_pwrdwn_common(cpu, state, plat_power_state[cpu]); 258 } 259 260 if (IS_MCUSYS_OFF_STATE(state)) { 261 /* Perform the common mcusys specific operations */ 262 plat_mcusys_pwrdwn_common(cpu, state, plat_power_state[cpu]); 263 } 264 } 265 266 static void plat_power_domain_suspend_finish(const psci_power_state_t *state) 267 { 268 unsigned int cpu = plat_my_core_pos(); 269 270 assert(cpu < PLATFORM_CORE_COUNT); 271 272 if (IS_MCUSYS_OFF_STATE(state)) { 273 /* Perform the common mcusys specific operations */ 274 plat_mcusys_pwron_common(cpu, state, plat_power_state[cpu]); 275 } 276 277 if (IS_CLUSTER_OFF_STATE(state)) { 278 /* Perform the common cluster specific operations */ 279 plat_cluster_pwron_common(cpu, state, plat_power_state[cpu]); 280 } 281 282 /* Perform the common CPU specific operations */ 283 plat_cpu_pwron_common(cpu, state, plat_power_state[cpu]); 284 285 plat_mt_pm_invoke_no_check(pwr_reflect, cpu, state); 286 } 287 288 static int plat_validate_power_state(unsigned int power_state, 289 psci_power_state_t *req_state) 290 { 291 unsigned int pstate = psci_get_pstate_type(power_state); 292 unsigned int aff_lvl = psci_get_pstate_pwrlvl(power_state); 293 unsigned int cpu = plat_my_core_pos(); 294 295 if (aff_lvl > PLAT_MAX_PWR_LVL) { 296 return PSCI_E_INVALID_PARAMS; 297 } 298 299 if (pstate == PSTATE_TYPE_STANDBY) { 300 req_state->pwr_domain_state[0] = PLAT_MAX_RET_STATE; 301 } else { 302 unsigned int i; 303 unsigned int pstate_id = psci_get_pstate_id(power_state); 304 plat_local_state_t s = MTK_LOCAL_STATE_OFF; 305 306 /* Use pstate_id to be power domain state */ 307 if (pstate_id > s) { 308 s = (plat_local_state_t)pstate_id; 309 } 310 311 for (i = 0U; i <= aff_lvl; i++) { 312 req_state->pwr_domain_state[i] = s; 313 } 314 } 315 316 plat_power_state[cpu] = power_state; 317 return PSCI_E_SUCCESS; 318 } 319 320 static void plat_get_sys_suspend_power_state(psci_power_state_t *req_state) 321 { 322 unsigned int lv; 323 unsigned int cpu = plat_my_core_pos(); 324 325 for (lv = PSCI_CPU_PWR_LVL; lv <= PLAT_MAX_PWR_LVL; lv++) { 326 req_state->pwr_domain_state[lv] = PLAT_MAX_OFF_STATE; 327 } 328 329 plat_power_state[cpu] = 330 psci_make_powerstate( 331 MT_PLAT_PWR_STATE_SYSTEM_SUSPEND, 332 PSTATE_TYPE_POWERDOWN, PLAT_MAX_PWR_LVL); 333 334 flush_dcache_range((uintptr_t) 335 &plat_power_state[cpu], 336 sizeof(plat_power_state[cpu])); 337 } 338 339 /******************************************************************************* 340 * MTK handlers to shutdown/reboot the system 341 ******************************************************************************/ 342 static void __dead2 plat_mtk_system_reset(void) 343 { 344 struct bl_aux_gpio_info *gpio_reset = plat_get_mtk_gpio_reset(); 345 346 INFO("MTK System Reset\n"); 347 348 gpio_set_value(gpio_reset->index, gpio_reset->polarity); 349 350 wfi(); 351 ERROR("MTK System Reset: operation not handled.\n"); 352 panic(); 353 } 354 355 static void __dead2 plat_mtk_system_off(void) 356 { 357 INFO("MTK System Off\n"); 358 359 rtc_power_off_sequence(); 360 pmic_power_off(); 361 362 wfi(); 363 ERROR("MTK System Off: operation not handled.\n"); 364 panic(); 365 } 366 367 static const plat_psci_ops_t plat_psci_ops = { 368 .system_reset = plat_mtk_system_reset, 369 .system_off = plat_mtk_system_off, 370 .cpu_standby = plat_cpu_standby, 371 .pwr_domain_on = plat_power_domain_on, 372 .pwr_domain_on_finish = plat_power_domain_on_finish, 373 .pwr_domain_off = plat_power_domain_off, 374 .pwr_domain_suspend = plat_power_domain_suspend, 375 .pwr_domain_suspend_finish = plat_power_domain_suspend_finish, 376 .validate_power_state = plat_validate_power_state, 377 .get_sys_suspend_power_state = plat_get_sys_suspend_power_state 378 }; 379 380 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 381 const plat_psci_ops_t **psci_ops) 382 { 383 *psci_ops = &plat_psci_ops; 384 secure_entrypoint = sec_entrypoint; 385 386 /* 387 * init the warm reset config for boot CPU 388 * reset arch as AARCH64 389 * reset addr as function bl31_warm_entrypoint() 390 */ 391 mcucfg_init_archstate(0U, 0U, true); 392 mcucfg_set_bootaddr(0U, 0U, secure_entrypoint); 393 394 spmc_init(); 395 plat_mt_pm = mt_plat_cpu_pm_init(); 396 397 return 0; 398 } 399