1 /* 2 * Copyright (c) 2021, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stddef.h> 8 9 #include <assert.h> 10 #include <common/debug.h> 11 #include <lib/mmio.h> 12 13 #include <mt_spm.h> 14 #include <mt_spm_internal.h> 15 #include <mt_spm_pmic_wrap.h> 16 #include <mt_spm_reg.h> 17 #include <mt_spm_resource_req.h> 18 #include <platform_def.h> 19 #include <plat_pm.h> 20 21 /************************************** 22 * Define and Declare 23 **************************************/ 24 #define ROOT_CORE_ADDR_OFFSET 0x20000000 25 #define SPM_WAKEUP_EVENT_MASK_CLEAN_MASK 0xefffffff 26 #define SPM_INIT_DONE_US 20 27 #define SPM_WAKEUP_REASON_MISSING 0xdeaddead 28 29 static unsigned int mt_spm_bblpm_cnt; 30 31 const char *wakeup_src_str[32] = { 32 [0] = "PCM_TIMER", 33 [1] = "RESERVED_DEBUG_B", 34 [2] = "KEYPAD", 35 [3] = "APWDT", 36 [4] = "APXGPT", 37 [5] = "MSDC", 38 [6] = "EINT", 39 [7] = "IRRX", 40 [8] = "ETHERNET_QOS", 41 [9] = "RESERVE0", 42 [10] = "SSPM", 43 [11] = "SCP", 44 [12] = "ADSP", 45 [13] = "SPM_WDT", 46 [14] = "USB_U2", 47 [15] = "USB_TOP", 48 [16] = "SYS_TIMER", 49 [17] = "EINT_SECURE", 50 [18] = "HDMI", 51 [19] = "RESERVE1", 52 [20] = "AFE", 53 [21] = "THERMAL", 54 [22] = "SYS_CIRQ", 55 [23] = "NNA2INFRA", 56 [24] = "CSYSPWREQ", 57 [25] = "RESERVE2", 58 [26] = "PCIE", 59 [27] = "SEJ", 60 [28] = "SPM_CPU_WAKEUPEVENT", 61 [29] = "APUSYS", 62 [30] = "RESERVE3", 63 [31] = "RESERVE4", 64 }; 65 66 /************************************** 67 * Function and API 68 **************************************/ 69 70 wake_reason_t __spm_output_wake_reason(int state_id, 71 const struct wake_status *wakesta) 72 { 73 uint32_t i, bk_vtcxo_dur, spm_26m_off_pct = 0U; 74 char *spm_26m_sta = NULL; 75 wake_reason_t wr = WR_UNKNOWN; 76 77 if (wakesta == NULL) { 78 return WR_UNKNOWN; 79 } 80 81 spm_26m_sta = ((wakesta->debug_flag & SPM_DBG_DEBUG_IDX_26M_SLEEP) == 0U) ? "on" : "off"; 82 83 if (wakesta->abort != 0U) { 84 ERROR("spmfw flow is aborted: 0x%x, timer_out = %u, 26M(%s)\n", 85 wakesta->abort, wakesta->timer_out, spm_26m_sta); 86 } else if (wakesta->r12 == SPM_WAKEUP_REASON_MISSING) { 87 WARN("cannot find wake up reason, timer_out = %u, 26M(%s)\n", 88 wakesta->timer_out, spm_26m_sta); 89 } else { 90 for (i = 0U; i < 32U; i++) { 91 if ((wakesta->r12 & (1U << i)) != 0U) { 92 INFO("wake up by %s, timer_out = %u, 26M(%s)\n", 93 wakeup_src_str[i], wakesta->timer_out, spm_26m_sta); 94 wr = WR_WAKE_SRC; 95 break; 96 } 97 } 98 } 99 100 INFO("r12 = 0x%x, r12_ext = 0x%x, r13 = 0x%x, debug_flag = 0x%x 0x%x\n", 101 wakesta->r12, wakesta->r12_ext, wakesta->r13, wakesta->debug_flag, 102 wakesta->debug_flag1); 103 INFO("raw_sta = 0x%x 0x%x 0x%x, idle_sta = 0x%x, cg_check_sta = 0x%x\n", 104 wakesta->raw_sta, wakesta->md32pcm_wakeup_sta, 105 wakesta->md32pcm_event_sta, wakesta->idle_sta, 106 wakesta->cg_check_sta); 107 INFO("req_sta = 0x%x 0x%x 0x%x 0x%x 0x%x, isr = 0x%x\n", 108 wakesta->req_sta0, wakesta->req_sta1, wakesta->req_sta2, 109 wakesta->req_sta3, wakesta->req_sta4, wakesta->isr); 110 INFO("rt_req_sta0 = 0x%x, rt_req_sta1 = 0x%x, rt_req_sta2 = 0x%x\n", 111 wakesta->rt_req_sta0, wakesta->rt_req_sta1, wakesta->rt_req_sta2); 112 INFO("rt_req_sta3 = 0x%x, dram_sw_con_3 = 0x%x, raw_ext_sta = 0x%x\n", 113 wakesta->rt_req_sta3, wakesta->rt_req_sta4, wakesta->raw_ext_sta); 114 INFO("wake_misc = 0x%x, pcm_flag = 0x%x 0x%x 0x%x 0x%x, req = 0x%x\n", 115 wakesta->wake_misc, wakesta->sw_flag0, wakesta->sw_flag1, 116 wakesta->b_sw_flag0, wakesta->b_sw_flag1, wakesta->src_req); 117 INFO("clk_settle = 0x%x, wlk_cntcv_l = 0x%x, wlk_cntcv_h = 0x%x\n", 118 wakesta->clk_settle, mmio_read_32(SYS_TIMER_VALUE_L), 119 mmio_read_32(SYS_TIMER_VALUE_H)); 120 121 if (wakesta->timer_out != 0U) { 122 bk_vtcxo_dur = mmio_read_32(SPM_BK_VTCXO_DUR); 123 spm_26m_off_pct = (100 * bk_vtcxo_dur) / wakesta->timer_out; 124 INFO("spm_26m_off_pct = %u\n", spm_26m_off_pct); 125 } 126 127 return wr; 128 } 129 130 void __spm_set_cpu_status(unsigned int cpu) 131 { 132 uint32_t root_core_addr; 133 134 if (cpu < 8U) { 135 mmio_write_32(ROOT_CPUTOP_ADDR, (1U << cpu)); 136 root_core_addr = SPM_CPU0_PWR_CON + (cpu * 0x4); 137 root_core_addr += ROOT_CORE_ADDR_OFFSET; 138 mmio_write_32(ROOT_CORE_ADDR, root_core_addr); 139 /* Notify MCUPM that preferred cpu wakeup */ 140 mmio_write_32(MCUPM_MBOX_WAKEUP_CPU, cpu); 141 } else { 142 ERROR("%s: error cpu number %d\n", __func__, cpu); 143 } 144 } 145 146 void __spm_src_req_update(const struct pwr_ctrl *pwrctrl, 147 unsigned int resource_usage) 148 { 149 uint8_t apsrc_req = ((resource_usage & MT_SPM_DRAM_S0) != 0U) ? 150 1 : pwrctrl->reg_spm_apsrc_req; 151 uint8_t ddr_en_req = ((resource_usage & MT_SPM_DRAM_S1) != 0U) ? 152 1 : pwrctrl->reg_spm_ddr_en_req; 153 uint8_t vrf18_req = ((resource_usage & MT_SPM_SYSPLL) != 0U) ? 154 1 : pwrctrl->reg_spm_vrf18_req; 155 uint8_t infra_req = ((resource_usage & MT_SPM_INFRA) != 0U) ? 156 1 : pwrctrl->reg_spm_infra_req; 157 uint8_t f26m_req = ((resource_usage & 158 (MT_SPM_26M | MT_SPM_XO_FPM)) != 0U) ? 159 1 : pwrctrl->reg_spm_f26m_req; 160 161 mmio_write_32(SPM_SRC_REQ, 162 ((apsrc_req & 0x1) << 0) | 163 ((f26m_req & 0x1) << 1) | 164 ((infra_req & 0x1) << 3) | 165 ((vrf18_req & 0x1) << 4) | 166 ((ddr_en_req & 0x1) << 7) | 167 ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) | 168 ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) | 169 ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) | 170 ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) | 171 ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12)); 172 } 173 174 void __spm_set_power_control(const struct pwr_ctrl *pwrctrl) 175 { 176 /* Auto-gen Start */ 177 178 /* SPM_AP_STANDBY_CON */ 179 mmio_write_32(SPM_AP_STANDBY_CON, 180 ((pwrctrl->reg_wfi_op & 0x1) << 0) | 181 ((pwrctrl->reg_wfi_type & 0x1) << 1) | 182 ((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) | 183 ((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) | 184 ((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) | 185 ((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) | 186 ((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) | 187 ((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29)); 188 189 /* SPM_SRC_REQ */ 190 mmio_write_32(SPM_SRC_REQ, 191 ((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) | 192 ((pwrctrl->reg_spm_f26m_req & 0x1) << 1) | 193 ((pwrctrl->reg_spm_infra_req & 0x1) << 3) | 194 ((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) | 195 ((pwrctrl->reg_spm_ddr_en_req & 0x1) << 7) | 196 ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) | 197 ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) | 198 ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) | 199 ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) | 200 ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12)); 201 202 /* SPM_SRC_MASK */ 203 mmio_write_32(SPM_SRC_MASK, 204 ((pwrctrl->reg_sspm_srcclkena_0_mask_b & 0x1) << 0) | 205 ((pwrctrl->reg_sspm_infra_req_0_mask_b & 0x1) << 1) | 206 ((pwrctrl->reg_sspm_apsrc_req_0_mask_b & 0x1) << 2) | 207 ((pwrctrl->reg_sspm_vrf18_req_0_mask_b & 0x1) << 3) | 208 ((pwrctrl->reg_sspm_ddr_en_0_mask_b & 0x1) << 4) | 209 ((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 5) | 210 ((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 6) | 211 ((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 7) | 212 ((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 8) | 213 ((pwrctrl->reg_scp_ddr_en_mask_b & 0x1) << 9) | 214 ((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 10) | 215 ((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 11) | 216 ((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 12) | 217 ((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 13) | 218 ((pwrctrl->reg_audio_dsp_ddr_en_mask_b & 0x1) << 14) | 219 ((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 15) | 220 ((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 16) | 221 ((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 17) | 222 ((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 18) | 223 ((pwrctrl->reg_apu_ddr_en_mask_b & 0x1) << 19) | 224 ((pwrctrl->reg_cpueb_srcclkena_mask_b & 0x1) << 20) | 225 ((pwrctrl->reg_cpueb_infra_req_mask_b & 0x1) << 21) | 226 ((pwrctrl->reg_cpueb_apsrc_req_mask_b & 0x1) << 22) | 227 ((pwrctrl->reg_cpueb_vrf18_req_mask_b & 0x1) << 23) | 228 ((pwrctrl->reg_cpueb_ddr_en_mask_b & 0x1) << 24) | 229 ((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 25) | 230 ((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 26) | 231 ((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 27) | 232 ((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 28) | 233 ((pwrctrl->reg_bak_psri_ddr_en_mask_b & 0x1) << 29)); 234 235 /* SPM_SRC2_MASK */ 236 mmio_write_32(SPM_SRC2_MASK, 237 ((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 0) | 238 ((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 1) | 239 ((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 2) | 240 ((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 3) | 241 ((pwrctrl->reg_msdc0_ddr_en_mask_b & 0x1) << 4) | 242 ((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 5) | 243 ((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 6) | 244 ((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 7) | 245 ((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 8) | 246 ((pwrctrl->reg_msdc1_ddr_en_mask_b & 0x1) << 9) | 247 ((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 10) | 248 ((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 11) | 249 ((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 12) | 250 ((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 13) | 251 ((pwrctrl->reg_msdc2_ddr_en_mask_b & 0x1) << 14) | 252 ((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 15) | 253 ((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 16) | 254 ((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 17) | 255 ((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 18) | 256 ((pwrctrl->reg_ufs_ddr_en_mask_b & 0x1) << 19) | 257 ((pwrctrl->reg_usb_srcclkena_mask_b & 0x1) << 20) | 258 ((pwrctrl->reg_usb_infra_req_mask_b & 0x1) << 21) | 259 ((pwrctrl->reg_usb_apsrc_req_mask_b & 0x1) << 22) | 260 ((pwrctrl->reg_usb_vrf18_req_mask_b & 0x1) << 23) | 261 ((pwrctrl->reg_usb_ddr_en_mask_b & 0x1) << 24) | 262 ((pwrctrl->reg_pextp_p0_srcclkena_mask_b & 0x1) << 25) | 263 ((pwrctrl->reg_pextp_p0_infra_req_mask_b & 0x1) << 26) | 264 ((pwrctrl->reg_pextp_p0_apsrc_req_mask_b & 0x1) << 27) | 265 ((pwrctrl->reg_pextp_p0_vrf18_req_mask_b & 0x1) << 28) | 266 ((pwrctrl->reg_pextp_p0_ddr_en_mask_b & 0x1) << 29)); 267 268 /* SPM_SRC3_MASK */ 269 mmio_write_32(SPM_SRC3_MASK, 270 ((pwrctrl->reg_pextp_p1_srcclkena_mask_b & 0x1) << 0) | 271 ((pwrctrl->reg_pextp_p1_infra_req_mask_b & 0x1) << 1) | 272 ((pwrctrl->reg_pextp_p1_apsrc_req_mask_b & 0x1) << 2) | 273 ((pwrctrl->reg_pextp_p1_vrf18_req_mask_b & 0x1) << 3) | 274 ((pwrctrl->reg_pextp_p1_ddr_en_mask_b & 0x1) << 4) | 275 ((pwrctrl->reg_gce0_infra_req_mask_b & 0x1) << 5) | 276 ((pwrctrl->reg_gce0_apsrc_req_mask_b & 0x1) << 6) | 277 ((pwrctrl->reg_gce0_vrf18_req_mask_b & 0x1) << 7) | 278 ((pwrctrl->reg_gce0_ddr_en_mask_b & 0x1) << 8) | 279 ((pwrctrl->reg_gce1_infra_req_mask_b & 0x1) << 9) | 280 ((pwrctrl->reg_gce1_apsrc_req_mask_b & 0x1) << 10) | 281 ((pwrctrl->reg_gce1_vrf18_req_mask_b & 0x1) << 11) | 282 ((pwrctrl->reg_gce1_ddr_en_mask_b & 0x1) << 12) | 283 ((pwrctrl->reg_spm_srcclkena_reserved_mask_b & 0x1) << 13) | 284 ((pwrctrl->reg_spm_infra_req_reserved_mask_b & 0x1) << 14) | 285 ((pwrctrl->reg_spm_apsrc_req_reserved_mask_b & 0x1) << 15) | 286 ((pwrctrl->reg_spm_vrf18_req_reserved_mask_b & 0x1) << 16) | 287 ((pwrctrl->reg_spm_ddr_en_reserved_mask_b & 0x1) << 17) | 288 ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 18) | 289 ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 19) | 290 ((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 20) | 291 ((pwrctrl->reg_disp1_ddr_en_mask_b & 0x1) << 21) | 292 ((pwrctrl->reg_disp2_apsrc_req_mask_b & 0x1) << 22) | 293 ((pwrctrl->reg_disp2_ddr_en_mask_b & 0x1) << 23) | 294 ((pwrctrl->reg_disp3_apsrc_req_mask_b & 0x1) << 24) | 295 ((pwrctrl->reg_disp3_ddr_en_mask_b & 0x1) << 25) | 296 ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 26) | 297 ((pwrctrl->reg_infrasys_ddr_en_mask_b & 0x1) << 27)); 298 299 /* Mask MCUSYS request since SOC HW would check it */ 300 mmio_write_32(SPM_SRC4_MASK, 0x1fc0000); 301 302 /* SPM_WAKEUP_EVENT_MASK */ 303 mmio_write_32(SPM_WAKEUP_EVENT_MASK, 304 ((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0)); 305 306 /* SPM_WAKEUP_EVENT_EXT_MASK */ 307 mmio_write_32(SPM_WAKEUP_EVENT_EXT_MASK, 308 ((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0)); 309 310 /* Auto-gen End */ 311 } 312 313 void __spm_disable_pcm_timer(void) 314 { 315 mmio_clrsetbits_32(PCM_CON1, RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY); 316 } 317 318 void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl) 319 { 320 uint32_t val, mask; 321 322 /* toggle event counter clear */ 323 mmio_setbits_32(PCM_CON1, 324 SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB); 325 326 /* toggle for reset SYS TIMER start point */ 327 mmio_setbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB); 328 329 if (pwrctrl->timer_val_cust == 0U) { 330 val = pwrctrl->timer_val; 331 } else { 332 val = pwrctrl->timer_val_cust; 333 } 334 335 mmio_write_32(PCM_TIMER_VAL, val); 336 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_TIMER_EN_LSB); 337 338 /* unmask AP wakeup source */ 339 if (pwrctrl->wake_src_cust == 0U) { 340 mask = pwrctrl->wake_src; 341 } else { 342 mask = pwrctrl->wake_src_cust; 343 } 344 345 mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~mask); 346 347 /* unmask SPM ISR (keep TWAM setting) */ 348 mmio_setbits_32(SPM_IRQ_MASK, ISRM_RET_IRQ_AUX); 349 350 /* toggle event counter clear */ 351 mmio_clrsetbits_32(PCM_CON1, SPM_EVENT_COUNTER_CLR_LSB, 352 SPM_REGWR_CFG_KEY); 353 /* toggle for reset SYS TIMER start point */ 354 mmio_clrbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB); 355 } 356 357 void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl) 358 { 359 /* set PCM flags and data */ 360 if (pwrctrl->pcm_flags_cust_clr != 0U) { 361 pwrctrl->pcm_flags &= ~pwrctrl->pcm_flags_cust_clr; 362 } 363 364 if (pwrctrl->pcm_flags_cust_set != 0U) { 365 pwrctrl->pcm_flags |= pwrctrl->pcm_flags_cust_set; 366 } 367 368 if (pwrctrl->pcm_flags1_cust_clr != 0U) { 369 pwrctrl->pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr; 370 } 371 372 if (pwrctrl->pcm_flags1_cust_set != 0U) { 373 pwrctrl->pcm_flags1 |= pwrctrl->pcm_flags1_cust_set; 374 } 375 376 mmio_write_32(SPM_SW_FLAG_0, pwrctrl->pcm_flags); 377 mmio_write_32(SPM_SW_FLAG_1, pwrctrl->pcm_flags1); 378 mmio_write_32(SPM_SW_RSV_7, pwrctrl->pcm_flags); 379 mmio_write_32(SPM_SW_RSV_8, pwrctrl->pcm_flags1); 380 } 381 382 void __spm_get_wakeup_status(struct wake_status *wakesta, 383 unsigned int ext_status) 384 { 385 wakesta->tr.comm.r12 = mmio_read_32(SPM_BK_WAKE_EVENT); 386 wakesta->tr.comm.timer_out = mmio_read_32(SPM_BK_PCM_TIMER); 387 wakesta->tr.comm.r13 = mmio_read_32(PCM_REG13_DATA); 388 wakesta->tr.comm.req_sta0 = mmio_read_32(SRC_REQ_STA_0); 389 wakesta->tr.comm.req_sta1 = mmio_read_32(SRC_REQ_STA_1); 390 wakesta->tr.comm.req_sta2 = mmio_read_32(SRC_REQ_STA_2); 391 wakesta->tr.comm.req_sta3 = mmio_read_32(SRC_REQ_STA_3); 392 wakesta->tr.comm.req_sta4 = mmio_read_32(SRC_REQ_STA_4); 393 wakesta->tr.comm.debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0); 394 wakesta->tr.comm.debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1); 395 396 if ((ext_status & SPM_INTERNAL_STATUS_HW_S1) != 0U) { 397 wakesta->tr.comm.debug_flag |= (SPM_DBG_DEBUG_IDX_DDREN_WAKE | 398 SPM_DBG_DEBUG_IDX_DDREN_SLEEP); 399 mmio_write_32(PCM_WDT_LATCH_SPARE_0, 400 wakesta->tr.comm.debug_flag); 401 } 402 403 wakesta->tr.comm.b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7); 404 wakesta->tr.comm.b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8); 405 406 /* record below spm info for debug */ 407 wakesta->r12 = mmio_read_32(SPM_BK_WAKE_EVENT); 408 wakesta->r12_ext = mmio_read_32(SPM_WAKEUP_STA); 409 wakesta->raw_sta = mmio_read_32(SPM_WAKEUP_STA); 410 wakesta->raw_ext_sta = mmio_read_32(SPM_WAKEUP_EXT_STA); 411 wakesta->md32pcm_wakeup_sta = mmio_read_32(MD32PCM_WAKEUP_STA); 412 wakesta->md32pcm_event_sta = mmio_read_32(MD32PCM_EVENT_STA); 413 wakesta->src_req = mmio_read_32(SPM_SRC_REQ); 414 415 /* backup of SPM_WAKEUP_MISC */ 416 wakesta->wake_misc = mmio_read_32(SPM_BK_WAKE_MISC); 417 418 /* get sleep time, backup of PCM_TIMER_OUT */ 419 wakesta->timer_out = mmio_read_32(SPM_BK_PCM_TIMER); 420 421 /* get other SYS and co-clock status */ 422 wakesta->r13 = mmio_read_32(PCM_REG13_DATA); 423 wakesta->idle_sta = mmio_read_32(SUBSYS_IDLE_STA); 424 wakesta->req_sta0 = mmio_read_32(SRC_REQ_STA_0); 425 wakesta->req_sta1 = mmio_read_32(SRC_REQ_STA_1); 426 wakesta->req_sta2 = mmio_read_32(SRC_REQ_STA_2); 427 wakesta->req_sta3 = mmio_read_32(SRC_REQ_STA_3); 428 wakesta->req_sta4 = mmio_read_32(SRC_REQ_STA_4); 429 430 /* get HW CG check status */ 431 wakesta->cg_check_sta = mmio_read_32(SPM_CG_CHECK_STA); 432 433 /* get debug flag for PCM execution check */ 434 wakesta->debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0); 435 wakesta->debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1); 436 437 /* get backup SW flag status */ 438 wakesta->b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7); 439 wakesta->b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8); 440 441 wakesta->rt_req_sta0 = mmio_read_32(SPM_SW_RSV_2); 442 wakesta->rt_req_sta1 = mmio_read_32(SPM_SW_RSV_3); 443 wakesta->rt_req_sta2 = mmio_read_32(SPM_SW_RSV_4); 444 wakesta->rt_req_sta3 = mmio_read_32(SPM_SW_RSV_5); 445 wakesta->rt_req_sta4 = mmio_read_32(SPM_SW_RSV_6); 446 447 /* get ISR status */ 448 wakesta->isr = mmio_read_32(SPM_IRQ_STA); 449 450 /* get SW flag status */ 451 wakesta->sw_flag0 = mmio_read_32(SPM_SW_FLAG_0); 452 wakesta->sw_flag1 = mmio_read_32(SPM_SW_FLAG_1); 453 454 /* get CLK SETTLE */ 455 wakesta->clk_settle = mmio_read_32(SPM_CLK_SETTLE); 456 457 /* check abort */ 458 wakesta->abort = (wakesta->debug_flag & DEBUG_ABORT_MASK) | 459 (wakesta->debug_flag1 & DEBUG_ABORT_MASK_1); 460 } 461 462 void __spm_clean_after_wakeup(void) 463 { 464 mmio_write_32(SPM_BK_WAKE_EVENT, 465 mmio_read_32(SPM_WAKEUP_STA) | 466 mmio_read_32(SPM_BK_WAKE_EVENT)); 467 mmio_write_32(SPM_CPU_WAKEUP_EVENT, 0); 468 469 /* 470 * clean wakeup event raw status (for edge trigger event) 471 * bit[28] for cpu wake up event 472 */ 473 mmio_write_32(SPM_WAKEUP_EVENT_MASK, SPM_WAKEUP_EVENT_MASK_CLEAN_MASK); 474 475 /* clean ISR status (except TWAM) */ 476 mmio_setbits_32(SPM_IRQ_MASK, ISRM_ALL_EXC_TWAM); 477 mmio_write_32(SPM_IRQ_STA, ISRC_ALL_EXC_TWAM); 478 mmio_write_32(SPM_SWINT_CLR, PCM_SW_INT_ALL); 479 } 480 481 void __spm_set_pcm_wdt(int en) 482 { 483 mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_EN_LSB, 484 SPM_REGWR_CFG_KEY); 485 486 if (en == 1) { 487 mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_WAKE_LSB, 488 SPM_REGWR_CFG_KEY); 489 490 if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) { 491 mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX); 492 } 493 494 mmio_write_32(PCM_WDT_VAL, 495 mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT); 496 mmio_setbits_32(PCM_CON1, 497 SPM_REGWR_CFG_KEY | RG_PCM_WDT_EN_LSB); 498 } 499 } 500 501 void __spm_send_cpu_wakeup_event(void) 502 { 503 /* SPM will clear SPM_CPU_WAKEUP_EVENT */ 504 mmio_write_32(SPM_CPU_WAKEUP_EVENT, 1); 505 } 506 507 void __spm_ext_int_wakeup_req_clr(void) 508 { 509 mmio_write_32(EXT_INT_WAKEUP_REQ_CLR, mmio_read_32(ROOT_CPUTOP_ADDR)); 510 511 /* Clear spm2mcupm wakeup interrupt status */ 512 mmio_write_32(SPM2CPUEB_CON, 0); 513 } 514 515 void __spm_xo_soc_bblpm(int en) 516 { 517 if (en == 1) { 518 mmio_clrsetbits_32(RC_M00_SRCLKEN_CFG, 519 RC_SW_SRCLKEN_FPM, RC_SW_SRCLKEN_RC); 520 assert(mt_spm_bblpm_cnt == 0); 521 mt_spm_bblpm_cnt += 1; 522 } else { 523 mmio_clrsetbits_32(RC_M00_SRCLKEN_CFG, 524 RC_SW_SRCLKEN_RC, RC_SW_SRCLKEN_FPM); 525 mt_spm_bblpm_cnt -= 1; 526 } 527 } 528 529 void __spm_hw_s1_state_monitor(int en, unsigned int *status) 530 { 531 unsigned int reg; 532 533 reg = mmio_read_32(SPM_ACK_CHK_CON_3); 534 535 if (en == 1) { 536 reg &= ~SPM_ACK_CHK_3_CON_CLR_ALL; 537 mmio_write_32(SPM_ACK_CHK_CON_3, reg); 538 reg |= SPM_ACK_CHK_3_CON_EN; 539 mmio_write_32(SPM_ACK_CHK_CON_3, reg); 540 } else { 541 if (((reg & SPM_ACK_CHK_3_CON_RESULT) != 0U) && 542 (status != NULL)) { 543 *status |= SPM_INTERNAL_STATUS_HW_S1; 544 } 545 546 mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, SPM_ACK_CHK_3_CON_EN, 547 SPM_ACK_CHK_3_CON_HW_MODE_TRIG | 548 SPM_ACK_CHK_3_CON_CLR_ALL); 549 } 550 } 551